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公开(公告)号：US4131945A
公开(公告)日：1978-12-26
申请号：US758120
申请日：1977-01-10
CPC分类号： G06F11/0757 , G06F13/285
摘要： A controller for directing a host machine which is operative to include a central processor for program execution, a system bus controlled by the central processor for carrying data, address and control signals, and a data memory coupled to the system bus. Additionally included is a direct memory access moudle for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update. Operative to interface with the above is a fault timer including a counter clocked at a given frequency for reset by the state signal from the direct memory access module if within a given period, and upon absence of reset for generating a fault signal, and a bistable unit operative to receive the fault signal from the counter for clocked latching thereof, and for generating a hold signal through the direct memory access module to the central processor and a disabling signal to the host machine.
摘要翻译： 一种用于引导主机的控制器，其操作以包括用于程序执行的中央处理器，由中央处理器控制的用于承载数据，地址和控制信号的系统总线以及耦合到系统总线的数据存储器。 还包括一个直接存储器访问模块，用于在接收到使能信号时通过系统总线将保持信号传输到中央处理器，并且在确认用于产生地址和状态信号的系统总线的控制假设时，该地址和状态信号将直接访问 用于主机更新的数据存储器。 与上述接口的操作是包括以给定频率计时的计数器的故障定时器，用于在给定时间段内由来自直接存储器存取模块的状态信号复位，以及在不存在用于产生故障信号的复位时，以及双稳态 单元，用于从计数器接收用于其时钟锁存的故障信号，并且用于通过直接存储器访问模块产生到中央处理器的保持信号和向主机的禁用信号。
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公开(公告)号：US4137565A
公开(公告)日：1979-01-30
申请号：US758117
申请日：1977-01-10
申请人： George E. Mager , Frank M. Nelson , Kenneth Gillett , Charles P. Holt , Edward L. Steiner , John W. Daughton , Kenton W. Fiske , Thomas Criswell , Warren L. Hall
发明人： George E. Mager , Frank M. Nelson , Kenneth Gillett , Charles P. Holt , Edward L. Steiner , John W. Daughton , Kenton W. Fiske , Thomas Criswell , Warren L. Hall
CPC分类号： G06F13/285 , G05B19/054 , G06F13/124 , G05B2219/1159 , G05B2219/14086 , G05B2219/14144 , G05B2219/15048 , G05B2219/15056
摘要： In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof. High-speed movement of data by the direct memory access system is achieved through dedicating a portion of random access memory in the central processing unit module for such accessing, and transferring control of the system bus from the central processing unit module to the direct memory access system. This enables data accessed through a fixed sequence of addresses from dedicated memory to be transferred directly to the host machine's control registers without incurring time constants that would otherwise be had if the data were to be manipulated by a central processor in the central processing unit module.
摘要翻译： 在诸如具有经由系统总线连接到输入 - 输出处理单元模块的中央处理单元模块的主机的控制器中，作为输入 - 输出处理单元模块的一部分而起作用的直接存储器存取系统 通过直接访问中央处理单元模块中的存储器来提供在主机中刷新和更新控制寄存器的高速装置。 可以对直接存储器存取系统进行编程，以与其正常模式同步刷新主机设备的控制寄存器，同时异步刷新 - 更新控制寄存器，如在周围的电敏周边的检测到的电气干扰的异常模式 控制寄存器，因此需要恢复。 通过直接存储器访问系统的高速数据移动是通过在中央处理单元模块中专用随机存取存储器的一部分进行这种访问来实现的，并且将系统总线从中央处理单元模块的控制转移到直接存储器访问 系统。 这使得能够通过来自专用存储器的固定地址序列访问的数据被直接传送到主机的控制寄存器，而不会产生如果数据由中央处理单元模块中的中央处理器来操纵的时间常数。
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公开(公告)号：US4131942A
公开(公告)日：1978-12-26
申请号：US758111
申请日：1977-01-10
申请人： Kenneth Gillett , Edward L. Steiner , Kenton W. Fiske , Kenneth A. Davis , William P. Kukucka , Thomas Criswell , Philip Richardson
发明人： Kenneth Gillett , Edward L. Steiner , Kenton W. Fiske , Kenneth A. Davis , William P. Kukucka , Thomas Criswell , Philip Richardson
CPC分类号： G06F13/285 , G06F1/28
摘要： A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller includes a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory. The module also includes an apparatus that is operative upon indication of a power down condition from the host machine for generating an enabling signal to the data memory while a current address signal on the system bus is being received by the data memory.
摘要翻译： 一种在控制器中使用的用于引导主机的多个控制寄存器的非易失性存储模块。 控制器包括通过具有控制数据的系统总线通信耦合的中央处理器，以及到模块和主机的地址线。 非易失性存储模块包括操作用于与系统总线接口以存储数据的数据存储器，以及根据中央处理器的命令通过系统总线从其输入输出数据。 另外，模块还包括耦合到数据存储器的电力存储单元，用于通过多个关键和非关键电力线将多个功率信号从主机分配到数据存储器，以提供可以是 在其中用于断电状态并且用于感测来自蓄电单元的关键电力线上的断电状态以将其切换到数据存储器。 该模块还包括一种在主机上指示掉电状态的装置，用于在数据存储器正在接收系统总线上的当前地址信号时向数据存储器产生使能信号。
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