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公开(公告)号：US20110125936A1
公开(公告)日：2011-05-26
申请号：US13014753
申请日：2011-01-27
IPC分类号： G06F13/28
CPC分类号： G06F13/128 , G06F13/28
摘要： A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor. For each data structure, a block of payload data is transferred from the data channel to a memory buffer using the DMA function when the data descriptor associated with the data structure is an eligible data descriptor that indicates the block of payload data is present, otherwise a dummy DMA transfer is performed when the data descriptor is an ineligible data descriptor that indicates no payload data is present in the associated data structure.
摘要翻译： 公开了一种通过在接收处理节点的CPU上传送连续的数据流而连续数据流的恒定数据速率信道发送异步数据脉冲串的系统和方法。 数据信道具有具有一个或多个数据结构的定义的帧结构，其中每个数据结构包括多个数据位置。 接收机从每个数据结构中的固定数据位置中选择数据作为每个相应数据结构的数据描述符。 接收器使用每个数据描述符配置直接存储器访问（DMA）功能。 对于每个数据结构，当与数据结构相关联的数据描述符是指示存在有效载荷数据块的合格数据描述符时，使用DMA功能将有效载荷数据块从数据信道传送到存储器缓冲器，否则为 当数据描述符是指示没有有效载荷数据存在于相关联的数据结构中的不合格数据描述符时，执行虚拟DMA传输。
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公开(公告)号：US08185672B2
公开(公告)日：2012-05-22
申请号：US13014753
申请日：2011-01-27
IPC分类号： G06F13/28
CPC分类号： G06F13/128 , G06F13/28
摘要： A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor. For each data structure, a block of payload data is transferred from the data channel to a memory buffer using the DMA function when the data descriptor associated with the data structure is an eligible data descriptor that indicates the block of payload data is present, otherwise a dummy DMA transfer is performed when the data descriptor is an ineligible data descriptor that indicates no payload data is present in the associated data structure.
摘要翻译： 公开了一种通过在接收处理节点的CPU上传送连续的数据流而连续数据流的恒定数据速率信道发送异步数据脉冲串的系统和方法。 数据信道具有具有一个或多个数据结构的定义的帧结构，其中每个数据结构包括多个数据位置。 接收机从每个数据结构中的固定数据位置中选择数据作为每个相应数据结构的数据描述符。 接收器使用每个数据描述符配置直接存储器访问（DMA）功能。 对于每个数据结构，当与数据结构相关联的数据描述符是指示存在有效载荷数据块的合格数据描述符时，使用DMA功能将有效载荷数据块从数据信道传送到存储器缓冲器，否则为 当数据描述符是指示没有有效载荷数据存在于相关联的数据结构中的不合格数据描述符时，执行虚拟DMA传输。
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公开(公告)号：US06310657B1
公开(公告)日：2001-10-30
申请号：US09679000
申请日：2000-10-04
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N550
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An on-screen display system in which a CPU generates windows in a working memory space also provides for real time calculation of window addresses in the working memory space. This can eliminate the need for a separate frame buffer memory.
摘要翻译： 其中CPU在工作存储器空间中生成窗口的屏幕显示系统还提供对工作存储器空间中的窗口地址的实时计算。 这可以消除对单独的帧缓冲存储器的需要。
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公开(公告)号：US06226291B1
公开(公告)日：2001-05-01
申请号：US08961764
申请日：1997-10-31
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits
IPC分类号： H04L1228
CPC分类号： H04N21/42653 , G09G5/14 , G09G5/395 , H04N5/44508 , H04N19/42 , H04N19/61 , H04N21/42615 , H04N21/42623 , H04N21/431 , H04N21/434 , H04N21/439 , H04N21/44 , H04N21/443
摘要： A transport stream parser system is provided that utilizes an intermediate buffer for containing packets after processing with an associated flag and then use a processor for further processing of packets selected by such flags.
摘要翻译： 提供了一种传输流解析器系统，其利用中间缓冲器在用关联的标志处理之后包含分组，然后使用处理器来进一步处理由这样的标志选择的分组。
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公开(公告)号：US06369855B1
公开(公告)日：2002-04-09
申请号：US08962514
申请日：1997-10-31
申请人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
发明人： Gerard Chauvel , Serge Lasserre , Mario Giani , Tiemen Spits , Gerard Benbassat , Frank L. Laczko, Sr. , Y. Paul Chiang , Karen L. Walker , Mark E. Paley , Brian O. Chae
IPC分类号： H04N726
CPC分类号： H04N21/8166 , G09G5/14 , G09G5/395 , G09G2340/04 , G09G2340/125 , G09G2360/02 , H04L29/06 , H04L69/22 , H04N5/44 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N7/0882 , H04N11/20 , H04N19/42 , H04N19/61 , H04N21/42204 , H04N21/426 , H04N21/42615 , H04N21/42623 , H04N21/42653 , H04N21/4305 , H04N21/431 , H04N21/4316 , H04N21/434 , H04N21/43632 , H04N21/439 , H04N21/44 , H04N21/443 , H04N21/47
摘要： An improved audio-visual circuit is provided that includes a transport packet parsing circuit for receiving a transport data packet stream, a CPU circuit for initializing said integrated circuit and for processing portions of said data packet stream, a ROM circuit for storing data, a RAM circuit for storing data, an audio decoder circuit for decoding audio portions of said data packet stream, a video decoder circuit for decoding video portions of said data packet stream, an NTSC/PAL encoding circuit for encoding video portions of said data packet stream, an OSD coprocessor circuit for processing OSD portions of said data packets, a traffic controller circuit moving portions of said data packet stream between portions of said integrated circuit, an extension bus interface circuit, a P1394 interface circuit, a communication coprocessors circuit, an address bus connected to said circuits, and a data bus connected to said circuits.
摘要翻译： 提供了一种改进的视听电路，其包括用于接收传输数据分组流的传输分组解析电路，用于初始化所述集成电路并用于处理所述数据分组流的部分的CPU电路，用于存储数据的ROM电路，RAM 用于存储数据的电路，用于解码所述数据分组流的音频部分的音频解码器电路，用于解码所述数据分组流的视频部分的视频解码器电路，用于对所述数据分组流的视频部分进行编码的NTSC / PAL编码电路， OSD协处理器电路，用于处理所述数据分组的OSD部分，业务控制器电路，在所述集成电路的部分之间移动所述数据分组流的部分，扩展总线接口电路，P1394接口电路，通信协处理器电路，连接的地址总线 连接到所述电路，以及连接到所述电路的数据总线。
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