公开(公告)号：US08358658B2

公开(公告)日：2013-01-22

申请号：US12727545

申请日：2010-03-19

申请人： William Thomas Flynn ,  Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： William Thomas Flynn ,  Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/28

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

公开(公告)号：US08416785B2

公开(公告)日：2013-04-09

申请号：US12764193

申请日：2010-04-21

申请人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk ,  Bruce Marshall Walk

发明人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk ,  Bruce Marshall Walk

IPC分类号： H04L12/28

CPC分类号： H04L47/34 ,  H04L45/245 ,  H04L49/552

摘要： A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在去除重影分组的同时在互连系统中实现源和目的设备之间的多个活动路径的方法和电路，以及提供了所述主题电路所在的设计结构。 每个分组包括生成ID，并且在源互连芯片中分配表示来自源设备的有序分组流中的分组位置的端到端（ETE）序列号。 分组从源互连芯片源传输到多个主动路径上的目的地互连芯片。 将接收到的分组的生成ID与目的地互连芯片上的当前生成ID进行比较，以验证分组接受。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收的接收数据包重新排序为正确的顺序。

公开(公告)号：US08340112B2

公开(公告)日：2012-12-25

申请号：US12731715

申请日：2010-03-25

申请人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/54

CPC分类号： G06F13/4022 ,  H04L49/1523 ,  H04L49/251 ,  H04L49/252

摘要： A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.

摘要翻译： 一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。 无头互连芯片包括切断开关和存储和正向开关。 从在无头互连芯片上的输出链路上传送的传入链路接收分组。 切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。

公开(公告)号：US20110235652A1

公开(公告)日：2011-09-29

申请号：US12731715

申请日：2010-03-25

申请人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/54 ,  G06F17/50

CPC分类号： G06F13/4022 ,  H04L49/1523 ,  H04L49/251 ,  H04L49/252

摘要： A method and circuit for implementing enhanced link bandwidth for a headless interconnect chip in a local rack interconnect system, and a design structure on which the subject circuit resides are provided. The headless interconnect chip includes a cut through switch and a store and forward switch. A packet is received from an incoming link to be transmitted on an outgoing link on the headless interconnect chip. Both the cut through switch and the store and forward switch are selectively used for moving packets received from the incoming link to the outgoing link on the headless interconnect chip.

摘要翻译： 一种用于实现本地机架互连系统中的无头互连芯片的增强的链路带宽的方法和电路，以及提供了所述主题电路所在的设计结构。 无头互连芯片包括切断开关和存储和正向开关。 从在无头互连芯片上的输出链路上传送的传入链路接收分组。 切断开关和存储和正向开关都有选择地用于将从进入链路接收的分组移动到无头互连芯片上的输出链路。