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1.发明授权公开(公告)号：US08652902B2
公开(公告)日：2014-02-18
申请号：US13410843
申请日：2012-03-02
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825
摘要： Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
摘要翻译： 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。
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2.发明申请公开(公告)号：US20120223378A1
公开(公告)日：2012-09-06
申请号：US13410843
申请日：2012-03-02
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/66825
摘要： Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.
摘要翻译： 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。
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公开(公告)号：US09425326B2
公开(公告)日：2016-08-23
申请号：US13981248
申请日：2012-01-24
IPC分类号： H01L29/792 , H01L29/66 , H01L29/10
CPC分类号： H01L29/792 , H01L29/1045 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
摘要翻译： 这里描述了一种用于形成垂直存储器件（150）的方法，该垂直存储器件具有夹在源区（109,112）和漏区（114）之间的垂直沟道区（113）。 在垂直沟道区域（113）的任一侧和相关的源极和漏极区域（109,112,114）之间提供电荷俘获层（106）。 源区（109,112）包括在包括具有第一掺杂浓度的第一掺杂类型的第一区域（109）和包括与第一掺杂类型相反的第二掺杂类型的第二区域（112）之间的结，并且 第二掺杂浓度。 漏区（114）包括具有第一掺杂浓度的第一掺杂型。 在另一个实施例中，漏区具有不同掺杂类型和浓度的两个区域，并且源极区域包括具有第一掺杂浓度的第一掺杂型。
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4.发明授权公开(公告)号：US08835278B2
公开(公告)日：2014-09-16
申请号：US13885884
申请日：2011-11-16
申请人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
发明人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L27/115
CPC分类号： H01L21/76224 , H01L21/76208 , H01L21/76281 , H01L21/823431 , H01L27/11521
摘要： Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.
摘要翻译： 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。
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5.发明申请公开(公告)号：US20140065794A1
公开(公告)日：2014-03-06
申请号：US13885884
申请日：2011-11-16
申请人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
发明人： Gouri Sankar Kar , Antonino Cacciato , Min-Soo Kim
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76208 , H01L21/76281 , H01L21/823431 , H01L27/11521
摘要： Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.
摘要翻译： 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。
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公开(公告)号：US20130341702A1
公开(公告)日：2013-12-26
申请号：US13981248
申请日：2012-01-24
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L29/1045 , H01L29/66666 , H01L29/66833 , H01L29/7926
摘要： Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
摘要翻译： 这里描述了一种用于形成垂直存储器件（150）的方法，该垂直存储器件具有夹在源区（109,112）和漏区（114）之间的垂直沟道区（113）。 在垂直沟道区域（113）的任一侧和相关的源极和漏极区域（109,112,114）之间提供电荷俘获层（106）。 源区（109,112）包括在包括具有第一掺杂浓度的第一掺杂类型的第一区域（109）和包括与第一掺杂类型相反的第二掺杂类型的第二区域（112）之间的结，并且 第二掺杂浓度。 漏区（114）包括具有第一掺杂浓度的第一掺杂型。 在另一个实施例中，漏区具有不同掺杂类型和浓度的两个区域，并且源极区域包括具有第一掺杂浓度的第一掺杂型。
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