公开(公告)号：US08652902B2

公开(公告)日：2014-02-18

申请号：US13410843

申请日：2012-03-02

Applicant: Pieter Blomme ,  Antonino Cacciato ,  Gouri Sankar Kar

Inventor： Pieter Blomme ,  Antonino Cacciato ,  Gouri Sankar Kar

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract translation: 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。

公开(公告)号：US08138538B2

公开(公告)日：2012-03-20

申请号：US12249060

申请日：2008-10-10

Applicant: Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

Inventor： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC: H01L27/108

CPC classification number: H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract translation: 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。

公开(公告)号：US09425326B2

公开(公告)日：2016-08-23

申请号：US13981248

申请日：2012-01-24

Applicant: Gouri Sankar Kar ,  Antonino Cacciato

Inventor： Gouri Sankar Kar ,  Antonino Cacciato

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/792 ,  H01L29/1045 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.

Abstract translation: 这里描述了一种用于形成垂直存储器件（150）的方法，该垂直存储器件具有夹在源区（109,112）和漏区（114）之间的垂直沟道区（113）。 在垂直沟道区域（113）的任一侧和相关的源极和漏极区域（109,112,114）之间提供电荷俘获层（106）。 源区（109,112）包括在包括具有第一掺杂浓度的第一掺杂类型的第一区域（109）和包括与第一掺杂类型相反的第二掺杂类型的第二区域（112）之间的结，并且 第二掺杂浓度。 漏区（114）包括具有第一掺杂浓度的第一掺杂型。 在另一个实施例中，漏区具有不同掺杂类型和浓度的两个区域，并且源极区域包括具有第一掺杂浓度的第一掺杂型。

公开(公告)号：US20100090348A1

公开(公告)日：2010-04-15

申请号：US12249104

申请日：2008-10-10

Applicant: Inho Park ,  Hans-Peter Moll ,  Gouri Sankar Kar ,  Lars Heineck

Inventor： Inho Park ,  Hans-Peter Moll ,  Gouri Sankar Kar ,  Lars Heineck

IPC: H01L23/48 ,  H01L21/76 ,  H01L21/82

CPC classification number: H01L21/743

Abstract: An integrated circuit is manufactured from a semiconductor substrate having trenches with first and second sidewalls facing each other and a conductive line arranged in a bottom region of the trenches. At least the bottom region of the trenches is lined with an insulative material between the conductive line and the substrate. A first sacrificial layer is formed above the conductive line adjacent the first and second sidewalls. The trenches are filled with one or more additional sacrificial layers having a different etch selectivity than the first sacrificial layer. A portion of the one or more additional sacrificial layers and a portion of the insulative material are selectively removed to the first sacrificial layer so that the substrate is exposed below the first sacrificial layer along the first trench sidewalls and covered by the insulative material along the second trench sidewalls.

Abstract translation: 集成电路由具有第一和第二侧壁彼此面对的沟槽的半导体衬底和布置在沟槽的底部区域中的导电线制成。 沟槽的至少底部区域在导电线和衬底之间衬有绝缘材料。 第一牺牲层形成在与第一和第二侧壁相邻的导电线的上方。 沟槽填充有一个或多个具有与第一牺牲层不同的蚀刻选择性的附加牺牲层。 所述一个或多个附加牺牲层的一部分和所述绝缘材料的一部分被选择性地移除到所述第一牺牲层，使得所述衬底沿着所述第一沟槽侧壁暴露在所述第一牺牲层下方并且沿着所述第二牺牲层被所述绝缘材料覆盖 沟槽侧壁。

公开(公告)号：US08835278B2

公开(公告)日：2014-09-16

申请号：US13885884

申请日：2011-11-16

Applicant: Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

Inventor： Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L21/76224 ,  H01L21/76208 ,  H01L21/76281 ,  H01L21/823431 ,  H01L27/11521

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract translation: 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

公开(公告)号：US20140065794A1

公开(公告)日：2014-03-06

申请号：US13885884

申请日：2011-11-16

Applicant: Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

Inventor： Gouri Sankar Kar ,  Antonino Cacciato ,  Min-Soo Kim

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76208 ,  H01L21/76281 ,  H01L21/823431 ,  H01L27/11521

Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.

Abstract translation: 公开了在用于半导体器件的翅片下面形成局部埋置介质层的方法。 在一些实施例中，该方法可以包括提供包括体半导体材料并在衬底中形成至少两个沟槽的衬底，从而形成至少一个鳍。 该方法还包括用绝缘材料填充沟槽并且部分地去除绝缘材料以在每个沟槽的底部形成绝缘区域。 该方法还包括至少在沟槽的侧壁上沉积衬垫，从每个绝缘区域的顶部去除层，从而在鳍的底部区域形成窗口开口，并且将本体半导体材料 通过窗口打开翅片的底部区域，从而在翅片的底部区域中形成局部埋置的介质层。

公开(公告)号：US20130341702A1

公开(公告)日：2013-12-26

申请号：US13981248

申请日：2012-01-24

Applicant: Gouri Sankar Kar ,  Antonino Cacciato

Inventor： Gouri Sankar Kar ,  Antonino Cacciato

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L29/1045 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926

Abstract: Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.

Abstract translation: 这里描述了一种用于形成垂直存储器件（150）的方法，该垂直存储器件具有夹在源区（109,112）和漏区（114）之间的垂直沟道区（113）。 在垂直沟道区域（113）的任一侧和相关的源极和漏极区域（109,112,114）之间提供电荷俘获层（106）。 源区（109,112）包括在包括具有第一掺杂浓度的第一掺杂类型的第一区域（109）和包括与第一掺杂类型相反的第二掺杂类型的第二区域（112）之间的结，并且 第二掺杂浓度。 漏区（114）包括具有第一掺杂浓度的第一掺杂型。 在另一个实施例中，漏区具有不同掺杂类型和浓度的两个区域，并且源极区域包括具有第一掺杂浓度的第一掺杂型。

公开(公告)号：US20130341701A1

公开(公告)日：2013-12-26

申请号：US13877616

申请日：2011-10-06

Applicant: Pieter Blomme ,  Gouri Sankar Kar

Inventor： Pieter Blomme ,  Gouri Sankar Kar

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L21/764 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Disclosed are vertical semiconductor devices and methods of manufacturing vertical semiconductor devices. An example method includes providing a semiconductor substrate, and forming a stack of horizontal layers on the semiconductor substrate, where the horizontal layers are substantially parallel to a surface of the semiconductor substrate, and the horizontal layers comprise alternating conductive layers and dielectric layers. The method further includes forming a vertical channel region through the stack of horizontal layers, where the vertical channel region is substantially perpendicular to a surface of the semiconductor substrate, and the vertical channel region comprises sidewall surfaces. The method further includes forming a charge storage layer on regions of the sidewall surfaces of the vertical channel region that are in direct contact with conductive layers in the stack of horizontal layers and, at a distance from the vertical channel region, forming a vertical dielectric region through the stack of horizontal layers.

Abstract translation: 公开了垂直半导体器件和制造垂直半导体器件的方法。 示例性方法包括提供半导体衬底，并且在半导体衬底上形成水平层堆叠，其中水平层基本上平行于半导体衬底的表面，并且水平层包括交替的导电层和电介质层。 该方法还包括通过水平层的堆叠形成垂直沟道区域，其中垂直沟道区域基本上垂直于半导体衬底的表面，并且垂直沟道区域包括侧壁表面。 该方法还包括在垂直沟道区域的侧壁表面的与水平层堆叠中的导电层直接接触的区域上形成电荷存储层，并且在与垂直沟道区一定距离处形成垂直电介质区域 通过堆叠的水平层。

公开(公告)号：US20120223378A1

公开(公告)日：2012-09-06

申请号：US13410843

申请日：2012-03-02

Applicant: Pieter Blomme ,  Antonino Cacciato ,  Gouri Sankar Kar

Inventor： Pieter Blomme ,  Antonino Cacciato ,  Gouri Sankar Kar

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract translation: 公开了用于制造如此获得的浮动栅极存储器件和浮动栅极存储器件的方法。 在一个实施例中，公开了一种方法，其包括提供绝缘体上半导体衬底，在绝缘体上半导体衬底中形成至少两个沟槽，并且作为形成至少两个沟槽的结果，形成至少一个 升高的结构。 该方法还包括通过部分地填充至少两个沟槽，热氧化至少一个升高结构的顶部的侧壁表面，从而在至少两个沟槽的底部形成隔离区，从而在 至少暴露的侧壁表面; 以及在所述至少一个升高的结构，所述栅极介电层和所述隔离区域上形成导电层，以形成至少一个浮置栅极半导体存储器件。

公开(公告)号：US20100090264A1

公开(公告)日：2010-04-15

申请号：US12249060

申请日：2008-10-10

Applicant: Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

Inventor： Hans-Peter Moll ,  Gouri Sankar Kar ,  Martin Popp ,  Lars Heineck ,  Peter Lahnor ,  Arnd Scholz ,  Stefan Jakschik ,  Wolfgang Roesner ,  Gerhard Enders ,  Werner Graf ,  Peter Baars ,  Klaus Muemmler ,  Bernd Hintze ,  Andrei Josiek

IPC: H01L27/108 ,  H01L21/02

CPC classification number: H01L27/10891 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract translation: 一个实施例涉及形成在半导体主体上的集成电路，其具有在第一和第二晶体管的源/漏区之间的互连。 互连件包括布置在半导体本体表面下方的金属体。 接触元件建立金属体与第一和第二晶体管的源/漏区之间的电接触。 接触元件沿着第一和第二晶体管的源极/漏极区域之间的连接路径延伸。 还公开了其它方法，装置和系统。