公开(公告)号：US09030403B2

公开(公告)日：2015-05-12

申请号：US13650155

申请日：2012-10-12

Applicant: Pixtronix, Inc.

Inventor： Hajime Akimoto ,  Toshio Miyazawa

IPC: G09G5/00

CPC classification number: G09G5/00 ,  G09G3/2022 ,  G09G3/3433 ,  G09G2300/0473 ,  G09G2300/0809 ,  G09G2300/0823 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2300/0876 ,  G09G2310/0262

Abstract: A pixel circuit includes a first control electrode and a second control electrode between which a mechanical shutter is put, and a first control voltage application circuit for inputting a first control voltage to the first control electrode according to an image signal. The first control voltage application circuit includes an input transistor, a retaining capacitor and a first transistor. One of current terminals of the input transistor is connected to a signal line. A gate of the input transistor is connected to a scanning line. One terminal of the retaining capacitor is input with a capacitor control signal and the other terminal is connected to the input transistor. The first transistor has a gate connected to the retaining capacitor and two current terminals, one of which is connected to a first control electrode and the other of which is input with a first control signal.

Abstract translation: 像素电路包括第一控制电极和放置机械快门的第二控制电极，以及根据图像信号将第一控制电压输入到第一控制电极的第一控制电压施加电路。 第一控制电压施加电路包括输入晶体管，保持电容和第一晶体管。 输入晶体管的一个电流端子连接到信号线。 输入晶体管的栅极连接到扫描线。 保持电容器的一个端子输入电容器控制信号，另一个端子连接到输入晶体管。 第一晶体管具有连接到保持电容器的栅极和两个电流端子，其中一个连接到第一控制电极，另一个被输入第一控制信号。

公开(公告)号：US09099997B2

公开(公告)日：2015-08-04

申请号：US13651785

申请日：2012-10-15

Applicant: Pixtronix, Inc.

Inventor： Toshio Miyazawa ,  Hajime Akimoto

IPC: H03K3/356 ,  G09G3/34

CPC classification number: H03K5/153 ,  G09G3/2092 ,  G09G3/3433 ,  G09G2310/02 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/045 ,  H03K3/356113 ,  H03K2005/00078 ,  H03K2005/00215

Abstract: A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

Abstract translation: 提供一种能够控制排水雪崩效应并提高可靠性的锁存电路。 锁存电路包括输入晶体管，当扫描电压输入到栅极时，输入对应于“0”或“1”的电压，存储由输入晶体管引入的电压的存储电容，并具有第一电极和第二电极 第一电极被输入电容控制信号，第二电极连接到输入晶体管的第二电极，第一导电型第一晶体管具有连接到输入晶体管的第二电极的栅极，第二电极连接到 第一输出端子和具有第一锁存器控制信号的第一电极输入端和连接到第一晶体管的第二电极的栅极的第二导电型第二晶体管，连接到第二输出端子的第二电极和第一 电极输入具有第二锁存控制信号。

公开(公告)号：US20150295568A1

公开(公告)日：2015-10-15

申请号：US14752361

申请日：2015-06-26

Applicant: Pixtronix, Inc.

Inventor： Toshio Miyazawa ,  Hajime Akimoto

IPC: H03K5/153 ,  G09G3/34 ,  G09G3/20

CPC classification number: H03K5/153 ,  G09G3/2092 ,  G09G3/3433 ,  G09G2310/02 ,  G09G2310/0264 ,  G09G2310/0289 ,  G09G2310/0294 ,  G09G2310/08 ,  G09G2320/045 ,  H03K3/356113 ,  H03K2005/00078 ,  H03K2005/00215

Abstract: A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

Abstract translation: 提供一种能够控制排水雪崩效应并提高可靠性的锁存电路。 锁存电路包括输入晶体管，当扫描电压输入到栅极时，输入对应于“0”或“1”的电压，存储由输入晶体管引入的电压的存储电容，并具有第一电极和第二电极 第一电极被输入电容控制信号，第二电极连接到输入晶体管的第二电极，第一导电型第一晶体管具有连接到输入晶体管的第二电极的栅极，第二电极连接到 第一输出端子和具有第一锁存器控制信号的第一电极输入端和连接到第一晶体管的第二电极的栅极的第二导电型第二晶体管，连接到第二输出端子的第二电极和第一 电极输入具有第二锁存控制信号。