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公开(公告)号：US20120081165A1
公开(公告)日：2012-04-05
申请号：US12894210
申请日：2010-09-30
申请人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
发明人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
CPC分类号： H03K19/00315 , H03K19/018528
摘要： A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.
摘要翻译： 高耐压逆变器电路包括：第一PMOS晶体管，其源极连接到VDDQ，漏极连接到第一节点; 第二PMOS晶体管，源极连接到第一节点，漏极连接到输出端; 第一NMOS晶体管，源极连接到VSS，漏极连接到第二节点; 第二NMOS晶体管，源极连接到第二节点，漏极连接到输出。 第一PMOS晶体管的栅极由具有VDDQ和VSS之间的电压摆幅的第一信号控制。 第一NMOS晶体管和第二PMOS晶体管的栅极由具有在VDD和VSS之间的电压摆幅的第二信号控制。 VDD低于VDDQ。 第二NMOS晶体管的栅极以大于VSS的第一电压偏置。
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公开(公告)号：US20110273949A1
公开(公告)日：2011-11-10
申请号：US12774851
申请日：2010-05-06
申请人： Po-Hung CHEN , Sung-Chieh LIN , Kuoyuan HSU , Jiann-Tseng HUANG
发明人： Po-Hung CHEN , Sung-Chieh LIN , Kuoyuan HSU , Jiann-Tseng HUANG
IPC分类号： G11C17/16
摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
摘要翻译： 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。
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公开(公告)号：US20120020177A1
公开(公告)日：2012-01-26
申请号：US12839542
申请日：2010-07-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译： 一些实施例涉及具有多个行和列的存储器阵列。 列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。 行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。
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公开(公告)号：US20130107603A1
公开(公告)日：2013-05-02
申请号：US13285357
申请日：2011-10-31
IPC分类号： G11C17/16
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译： 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。
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公开(公告)号：US20130155799A1
公开(公告)日：2013-06-20
申请号：US13771674
申请日：2013-02-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译： 读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。 与节点耦合的页脚被打开。
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公开(公告)号：US20120320700A1
公开(公告)日：2012-12-20
申请号：US13595551
申请日：2012-08-27
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译： 本说明书涉及包括位线的电路。 电路还包括至少一个存储体。 所述至少一个存储体包括至少一个存储器单元，第一器件被配置为当所述至少一个存储器单元被激活时，在所述位线和所述至少一个存储器单元之间提供电流路径，以及被配置为减少 当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。 电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的次要电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。
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公开(公告)号：US20120086495A1
公开(公告)日：2012-04-12
申请号：US12900650
申请日：2010-10-08
申请人： Po-Hung CHEN , Kuoyuan (Peter) HSU , David YEN , Sung-Chieh LIN
发明人： Po-Hung CHEN , Kuoyuan (Peter) HSU , David YEN , Sung-Chieh LIN
IPC分类号： H03L5/00
CPC分类号： H03K3/356165
摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.
摘要翻译： 第一反相器的输入被配置为用作输入节点。 第一反相器的输出耦合到第二反相器的输入端。 第二反相器的输出被配置为用作输出节点。 第三反相器的输入耦合到第一反相器的输入端。 第一NMOS晶体管的栅极耦合到第三反相器的输出端。 第一NMOS晶体管的漏极耦合到第二反相器。 第一NMOS晶体管的源极被配置为用作电平输入节点。 当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。
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公开(公告)号：US20120057423A1
公开(公告)日：2012-03-08
申请号：US12877646
申请日：2010-09-08
IPC分类号： G11C17/16
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译： 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。
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9.发明申请公开(公告)号：US20120038410A1
公开(公告)日：2012-02-16
申请号：US12856824
申请日：2010-08-16
申请人： Wei-Li LIAO , Sung-Chieh LIN , Kuoyuan HSU
发明人： Wei-Li LIAO , Sung-Chieh LIN , Kuoyuan HSU
IPC分类号： H03K17/687
CPC分类号： G11C29/026 , G11C29/028
摘要： An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.
摘要翻译： 集成电路包括感测电路，保险丝盒和熔丝总线解码器。 感测电路包括输出节点，并且保险丝盒包括与多个电阻元件串联耦合的多个开关。 保险丝盒耦合到感测电路的输出节点，保险丝盒从该感应电路的输出节点配置为接收电流。 熔丝总线解码器耦合到保险丝盒，并且包括至少一个多路分解器，其被配置为接收信号，并且响应于输出多个控制信号，用于选择性地打开和闭合保险丝盒的开关以调整保险丝盒两端的电阻。 读出放大器的输出节点的电压基于保险丝盒和电流的电阻。
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公开(公告)号：US20120257435A1
公开(公告)日：2012-10-11
申请号：US13107441
申请日：2011-05-13
申请人： Sung-Chieh LIN , David YEN , Ian CHIU , Kuoyuan (Peter) HSU
发明人： Sung-Chieh LIN , David YEN , Ian CHIU , Kuoyuan (Peter) HSU
IPC分类号： G11C17/16 , H01L21/768 , H01L23/525
CPC分类号： H01L23/5256 , G11C17/10 , G11C17/16 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.
摘要翻译： 本文公开的方法和结构的实施例提供了形成和编程非水化多晶硅熔丝的机制。 非水银多晶硅熔丝和编程晶体管形成一个可编程的编程电压低的一次可编程（OTP）存储单元。
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