公开(公告)号：US08824234B2

公开(公告)日：2014-09-02

申请号：US13771674

申请日：2013-02-20

申请人： Sung-Chieh Lin ,  David Yen ,  Wei-Li Liao ,  Jiann-Tseng Huang ,  Kuoyuan (Peter) Hsu

发明人： Sung-Chieh Lin ,  David Yen ,  Wei-Li Liao ,  Jiann-Tseng Huang ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/16

CPC分类号： G11C17/16

摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.

摘要翻译： 读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。 与节点耦合的页脚被打开。

公开(公告)号：US08787109B2

公开(公告)日：2014-07-22

申请号：US13466518

申请日：2012-05-08

申请人： Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C16/06

CPC分类号： G11C8/08

摘要： A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.

摘要翻译： 一种字线驱动器，包括被配置为接收控制信号的控制开关，其中所述控制开关位于被配置为接收工作电压信号的第一节点和被配置为确定所述字线驱动器的输出的第二节点之间。 字线驱动器还包括电连接到第二节点的交叉耦合放大器。 字线驱动器还包括电连接到交叉耦合放大器的至少一个反相器。 包括字线驱动器和包括至少一个电子熔丝的存储器阵列的半导体器件。

公开(公告)号：US08625324B2

公开(公告)日：2014-01-07

申请号：US13107441

申请日：2011-05-13

申请人： Sung-Chieh Lin ,  David Yen ,  Chi-Hsu Chiu ,  Kuoyuan (Peter) Hsu

发明人： Sung-Chieh Lin ,  David Yen ,  Chi-Hsu Chiu ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/00 ,  H01L23/52

CPC分类号： H01L23/5256 ,  G11C17/10 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： The embodiments of methods and structures disclosed herein provide mechanisms of forming and programming a non-salicided polysilicon fuse. The non-salicided polysilicon fuse and a programming transistor form a one-time programmable (OTP) memory cell, which can be programmed with a low programming voltage.

摘要翻译： 本文公开的方法和结构的实施例提供了形成和编程非水化多晶硅熔丝的机制。 非水银多晶硅熔丝和编程晶体管形成一个可编程的编程电压低的一次可编程（OTP）存储单元。

公开(公告)号：US20130301374A1

公开(公告)日：2013-11-14

申请号：US13466518

申请日：2012-05-08

申请人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

发明人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A word line driver including a control switch configured to receive a control signal, where the control switch is between a first node configured to receive an operating voltage signal and a second node configured to determine an output of the word line driver. The word line driver further includes a cross-coupled amplifier electrically connected to the second node. The word line driver further includes at least one inverter electrically connected to the cross-coupled amplifier. A semiconductor device including the word line driver and a memory array including at least one electronic fuse.

摘要翻译： 一种字线驱动器，包括被配置为接收控制信号的控制开关，其中所述控制开关位于被配置为接收工作电压信号的第一节点和被配置为确定所述字线驱动器的输出的第二节点之间。 字线驱动器还包括电连接到第二节点的交叉耦合放大器。 字线驱动器还包括电连接到交叉耦合放大器的至少一个反相器。 包括字线驱动器和包括至少一个电子熔丝的存储器阵列的半导体器件。

公开(公告)号：US20130262962A1

公开(公告)日：2013-10-03

申请号：US13434588

申请日：2012-03-29

申请人： Yun-Han CHEN ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

发明人： Yun-Han CHEN ,  Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC分类号： G06F11/07 ,  G06F11/10 ,  H03M13/19

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/1008 ,  H03M13/19 ,  H03M13/6561

摘要： In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word.

摘要翻译： 在一种方法中，通过第一电路将多个比特以第一格式转换成第二格式。 通过第二电路，使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。 第一电路和第二电路在第一芯片中电耦合在一起。 多个位选自1）地址信息，单元数据信息和具有错误的存储单元的程序信息; 以及2）第一字的字数据信息和与第一字的字数据信息相对应的错误代码和校正信息。

公开(公告)号：US08542549B2

公开(公告)日：2013-09-24

申请号：US13205009

申请日：2011-08-08

申请人： Sung-Chieh Lin ,  Wei-Li Liao ,  Kuoyuan (Peter) Hsu

发明人： Sung-Chieh Lin ,  Wei-Li Liao ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： An electrical fuse (eFuse) bit cell includes a program transistor, a read transistor, and an eFuse. The program transistor has a first program terminal, a second program terminal, and a third program terminal. The read transistor has a first read terminal, a second read terminal, and a third read terminal. The eFuse has a first end and a second end. The first end, the first program terminal, and the second read terminal are coupled together. The read transistor is configured to be off and the program transistor is configured to be on when the eFuse bit cell is in a program mode. The program transistor is configured to be off and the read transistor is configured to be on when the eFuse bit cell is in a read mode.

摘要翻译： 电熔丝（eFuse）位单元包括程序晶体管，读晶体管和eFuse。 程序晶体管具有第一程序终端，第二程序终端和第三程序终端。 读取晶体管具有第一读取端子，第二读取端子和第三读取端子。 eFuse具有第一端和第二端。 第一端，第一程序终端和第二读终端耦合在一起。 读晶体管被配置为截止，并且当eFuse位单元处于编程模式时，程序晶体管被配置为导通。 程序晶体管被配置为截止，并且当eFuse位单元处于读取模式时，读取晶体管被配置为导通。

公开(公告)号：US20130038375A1

公开(公告)日：2013-02-14

申请号：US13205058

申请日：2011-08-08

申请人： Sung-Chieh LIN ,  Wei-Li LIAO ,  Kuoyuan (Peter) HSU

发明人： Sung-Chieh LIN ,  Wei-Li LIAO ,  Kuoyuan (Peter) HSU

IPC分类号： H03L5/00

CPC分类号： H03K3/356182

摘要： A circuit includes a power switch and a level shifter. The level shifter has a node and an assistant circuit. The node is configured to control the power switch. The assistant circuitry is coupled to the node and configured for the node to receive a first voltage value through the assistant circuit. The first voltage value is different from a second voltage value of an input signal received by the level shifter.

摘要翻译： 电路包括电源开关和电平转换器。 电平移位器具有节点和辅助电路。 该节点配置为控制电源开关。 辅助电路耦合到节点并且被配置用于节点通过辅助电路接收第一电压值。 第一电压值不同于由电平移位器接收的输入信号的第二电压值。

公开(公告)号：US20120038410A1

公开(公告)日：2012-02-16

申请号：US12856824

申请日：2010-08-16

申请人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan HSU

发明人： Wei-Li LIAO ,  Sung-Chieh LIN ,  Kuoyuan HSU

IPC分类号： H03K17/687

CPC分类号： G11C29/026 ,  G11C29/028

摘要： An integrated circuit includes a sensing circuit, a fuse box, and a fuse bus decoder. The sensing circuit includes an output node, and the fuse box includes a plurality of switches coupled in series with a plurality of resistive elements. The fuse box is coupled to the output node of the sensing circuit from which the fuse box is configured to receive a current. The fuse bus decoder is coupled to the fuse box and includes at least one demultiplexer configured to receive a signal and in response output a plurality of control signals for selectively opening and closing the switches of the fuse box to adjust a resistance across the fuse box. A voltage of the output node of the sense amplifier is based on a resistance the fuse box and the current.

摘要翻译： 集成电路包括感测电路，保险丝盒和熔丝总线解码器。 感测电路包括输出节点，并且保险丝盒包括与多个电阻元件串联耦合的多个开关。 保险丝盒耦合到感测电路的输出节点，保险丝盒从该感应电路的输出节点配置为接收电流。 熔丝总线解码器耦合到保险丝盒，并且包括至少一个多路分解器，其被配置为接收信号，并且响应于输出多个控制信号，用于选择性地打开和闭合保险丝盒的开关以调整保险丝盒两端的电阻。 读出放大器的输出节点的电压基于保险丝盒和电流的电阻。

公开(公告)号：US20110007542A1

公开(公告)日：2011-01-13

申请号：US12833131

申请日：2010-07-09

申请人： Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

发明人： Sung-Chieh LIN ,  Kuoyuan (Peter) HSU

IPC分类号： G11C17/00 ,  G11C29/00

CPC分类号： G11C17/16 ,  G11C17/14 ,  G11C29/08

摘要： A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.

摘要翻译： 一次性编程（OTP）存储器阵列分为用户部分和测试部分。 用户部分和测试部分中的单元格被配置为形成棋盘图案，即在列和行方向上具有一个用户单元和一个测试单元的重复。 在用户部分未编程的情况下，对测试部分进行编程，并对存储器阵列的用户和测试部分以及其他电路进行各种附加测试。 即使OTP用户部分未被编程或测试，根据本发明的实施例提供的测试可以提供包括用户部分的OTP存储器具有高质量（即，用户部分中的OTP单元）的非常高的概率 可以编程并正常工作。

公开(公告)号：US07733096B2

公开(公告)日：2010-06-08

申请号：US11731960

申请日：2007-04-02

申请人： Sung-Chieh Lin ,  Po-Hung Chen

发明人： Sung-Chieh Lin ,  Po-Hung Chen

IPC分类号： G01R31/02

CPC分类号： G11C29/02 ,  G11C17/165 ,  G11C29/027

摘要： A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.

摘要翻译： 提供一种测试用于存储器件的熔丝元件的方法。 第一测试探针电连接到存储器件的程序终端。 第二测试探针电连接到接地端子。 保险丝元件位于程序端子和接地端子之间的电路上。 第一和第二测试探针电连接到测试装置。 测试设备在程序终端和接地端子之间施加第一个电压。 第一电压的第一电流的至少一部分流过熔丝元件。 在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。 测量第一电流并用于评估熔丝元件的导电状态。