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公开(公告)号：US20120081165A1
公开(公告)日：2012-04-05
申请号：US12894210
申请日：2010-09-30
申请人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
发明人： Jiann-Tseng HUANG , Sung-Chieh LIN , Kuoyuan HSU , Po-Hung CHEN
CPC分类号： H03K19/00315 , H03K19/018528
摘要： A high voltage tolerative inverter circuit includes a first PMOS transistor with a source connected to VDDQ and drain connected to a first node; a second PMOS transistor with a source connected to the first node and a drain connected to an output; a first NMOS transistor with a source connected to VSS and a drain connected to a second node; a second NMOS transistor with a source connected to the second node and a drain connected to the output. A gate of the first PMOS transistor is controlled by a first signal having a voltage swing between VDDQ and VSS. A gate of the first NMOS transistor and the second PMOS transistor are controlled by a second signal having a voltage swing between VDD and VSS. VDD is lower than VDDQ. A gate of the second NMOS transistor is biased with a first voltage greater than VSS.
摘要翻译： 高耐压逆变器电路包括：第一PMOS晶体管，其源极连接到VDDQ，漏极连接到第一节点; 第二PMOS晶体管，源极连接到第一节点，漏极连接到输出端; 第一NMOS晶体管，源极连接到VSS，漏极连接到第二节点; 第二NMOS晶体管，源极连接到第二节点，漏极连接到输出。 第一PMOS晶体管的栅极由具有VDDQ和VSS之间的电压摆幅的第一信号控制。 第一NMOS晶体管和第二PMOS晶体管的栅极由具有在VDD和VSS之间的电压摆幅的第二信号控制。 VDD低于VDDQ。 第二NMOS晶体管的栅极以大于VSS的第一电压偏置。
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公开(公告)号：US20110273949A1
公开(公告)日：2011-11-10
申请号：US12774851
申请日：2010-05-06
申请人： Po-Hung CHEN , Sung-Chieh LIN , Kuoyuan HSU , Jiann-Tseng HUANG
发明人： Po-Hung CHEN , Sung-Chieh LIN , Kuoyuan HSU , Jiann-Tseng HUANG
IPC分类号： G11C17/16
摘要： A circuit includes a fuse and a sensing and control circuit. The fuse is coupled between a MOS transistor and a current source node. The sensing and control circuit is configured to receive a programming pulse and output a modified programming signal to the gate of the MOS transistor for programming the fuse. The modified programming signal has a pulse width based on a magnitude of a current through the first fuse.
摘要翻译： 电路包括熔丝和感测和控制电路。 熔丝耦合在MOS晶体管和电流源节点之间。 感测和控制电路被配置为接收编程脉冲并将修改的编程信号输出到MOS晶体管的栅极，以编程保险丝。 改进的编程信号具有基于通过第一保险丝的电流的幅度的脉冲宽度。
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公开(公告)号：US20100329055A1
公开(公告)日：2010-12-30
申请号：US12824652
申请日：2010-06-28
CPC分类号： G11C13/00 , G11C5/147 , G11C7/00 , G11C7/062 , G11C7/22 , G11C13/0004 , G11C13/004 , G11C16/26 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2013/0045
摘要： A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.
摘要翻译： 一种具有第一电路的电路，其被配置为接收输入电压并产生产生流过电阻器件的第一电流的第一电压和产生第二电流的第二电压; 电耦合到所述电阻装置并具有产生第三电流的第三电压的节点; 以及第二电路，被配置为产生具有指示电阻装置的逻辑状态的逻辑状态的第四电压。
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公开(公告)号：US20120020177A1
公开(公告)日：2012-01-26
申请号：US12839542
申请日：2010-07-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译： 一些实施例涉及具有多个行和列的存储器阵列。 列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。 行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。
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公开(公告)号：US20130107603A1
公开(公告)日：2013-05-02
申请号：US13285357
申请日：2011-10-31
IPC分类号： G11C17/16
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译： 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。
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公开(公告)号：US20130155799A1
公开(公告)日：2013-06-20
申请号：US13771674
申请日：2013-02-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： A method of reading an eFuse in a column of eFuse memory cells includes electrically disconnecting a first end of the eFuse from a first electrical path. A second electrical path between a second end of the eFuse and a node is activated to bypass a third electrical path, where the third electrical path includes a diode device between the second end of the eFuse and the node. A footer coupled with the node is turned on.
摘要翻译： 读取eFuse存储单元列中的eFuse的方法包括将eFuse的第一端与第一电路断开。 eFuse的第二端和节点之间的第二电路被激活以绕过第三电路，其中第三电路包括在eFuse的第二端和节点之间的二极管器件。 与节点耦合的页脚被打开。
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公开(公告)号：US20120320700A1
公开(公告)日：2012-12-20
申请号：US13595551
申请日：2012-08-27
摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a minor current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.
摘要翻译： 本说明书涉及包括位线的电路。 电路还包括至少一个存储体。 所述至少一个存储体包括至少一个存储器单元，第一器件被配置为当所述至少一个存储器单元被激活时，在所述位线和所述至少一个存储器单元之间提供电流路径，以及被配置为减少 当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。 电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的次要电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。
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