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1.
公开(公告)号:US20230209994A1
公开(公告)日:2023-06-29
申请号:US18086797
申请日:2022-12-22
Inventor: Hyungjun Kim , Yongyoung Noh , Junhyung Lim , Huihui Zhu
IPC: H10K85/50 , H10K59/125 , H10K71/10
CPC classification number: H10K85/50 , H10K59/125 , H10K71/10 , H10K10/462
Abstract: A thin-film transistor including: a gate electrode; a gate insulating layer that is in contact with the gate electrode; a semiconductor layer insulated from the gate electrode by the gate insulating layer; and a source electrode and a drain electrode that are in contact with the semiconductor layer, wherein the semiconductor layer includes a perovskite compound represented by Formula 1:
[A]2[B][X]6:Z Formula 1
wherein, in Formula 1,
A includes a monovalent organic-cation, a monovalent inorganic-cation, or a combination thereof,
B includes Sn4+,
X includes a monovalent anion, and
Z includes a metal cation or a metalloid cation.-
2.
公开(公告)号:US20240128421A1
公开(公告)日:2024-04-18
申请号:US18364399
申请日:2023-08-02
Inventor: Hyungjun Kim , Yongyoung Noh , Junhyung Lim , Ao Liu
IPC: H01L33/62 , H01L25/16 , H01L29/18 , H01L29/417 , H01L29/66 , H01L29/786
CPC classification number: H01L33/62 , H01L25/167 , H01L29/185 , H01L29/41733 , H01L29/66742 , H01L29/78696 , H01L2933/0066
Abstract: A display device includes: a substrate; a thin-film transistor on the substrate; and a light-emitting diode electrically connected to the thin-film transistor, wherein the thin-film transistor includes: a semiconductor layer in which a source region, a drain region, and a channel region are defined; a gate electrode insulated from the semiconductor layer and overlapping the semiconductor layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the semiconductor layer includes a crystallized metal chalcogenide including a transition metal and a chalcogen element and has a layered structure.
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公开(公告)号:US11335399B2
公开(公告)日:2022-05-17
申请号:US17011929
申请日:2020-09-03
Inventor: Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC: G11C11/41 , G06N3/08 , G11C11/412 , G11C11/418 , G11C11/419
Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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