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1.发明公开公开(公告)号：US20230209994A1
公开(公告)日：2023-06-29
申请号：US18086797
申请日：2022-12-22
发明人： Hyungjun Kim , Yongyoung Noh , Junhyung Lim , Huihui Zhu
IPC分类号： H10K85/50 , H10K59/125 , H10K71/10
CPC分类号： H10K85/50 , H10K59/125 , H10K71/10 , H10K10/462
摘要： A thin-film transistor including: a gate electrode; a gate insulating layer that is in contact with the gate electrode; a semiconductor layer insulated from the gate electrode by the gate insulating layer; and a source electrode and a drain electrode that are in contact with the semiconductor layer, wherein the semiconductor layer includes a perovskite compound represented by Formula 1:
[A]2[B][X]6:Z Formula 1
wherein, in Formula 1,
A includes a monovalent organic-cation, a monovalent inorganic-cation, or a combination thereof,
B includes Sn4+,
X includes a monovalent anion, and
Z includes a metal cation or a metalloid cation.-
2.发明公开公开(公告)号：US20240128421A1
公开(公告)日：2024-04-18
申请号：US18364399
申请日：2023-08-02
发明人： Hyungjun Kim , Yongyoung Noh , Junhyung Lim , Ao Liu
IPC分类号： H01L33/62 , H01L25/16 , H01L29/18 , H01L29/417 , H01L29/66 , H01L29/786
CPC分类号： H01L33/62 , H01L25/167 , H01L29/185 , H01L29/41733 , H01L29/66742 , H01L29/78696 , H01L2933/0066
摘要： A display device includes: a substrate; a thin-film transistor on the substrate; and a light-emitting diode electrically connected to the thin-film transistor, wherein the thin-film transistor includes: a semiconductor layer in which a source region, a drain region, and a channel region are defined; a gate electrode insulated from the semiconductor layer and overlapping the semiconductor layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the semiconductor layer includes a crystallized metal chalcogenide including a transition metal and a chalcogen element and has a layered structure.
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公开(公告)号：US11335399B2
公开(公告)日：2022-05-17
申请号：US17011929
申请日：2020-09-03
发明人： Jinseok Kim , Yulhwa Kim , Jae-Joon Kim , Hyungjun Kim
IPC分类号： G11C11/41 , G06N3/08 , G11C11/412 , G11C11/418 , G11C11/419
摘要： Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US12022690B2
公开(公告)日：2024-06-25
申请号：US17244857
申请日：2021-04-29
发明人： Jun Hyung Lim , Hyungjun Kim , Hyungjun Kim , Young Jun Kim , Ju Sang Park , Whang Je Woo
IPC分类号： H10K59/121 , H01L21/02 , H01L27/12 , H01L29/24 , H01L29/66 , H01L29/76 , H01L29/786 , H10K59/12 , H10K71/00
CPC分类号： H10K59/1213 , H10K71/00 , H01L21/02568 , H01L21/0262 , H01L27/1225 , H01L27/127 , H01L29/24 , H01L29/66969 , H01L29/7606 , H01L29/78696 , H10K59/1201
摘要： A method may be used for manufacturing a semiconductor element. The method may include the following steps: preparing a substrate; forming a semiconductor layer on the substrate, wherein the semiconductor layer includes crystallized two-dimensional layers; forming a source electrode and a drain electrode on the semiconductor layer; forming an semiconductor member by wet etching the semiconductor layer using sodium hypochlorite as an etchant, wherein the wet etching results in a residue; and removing the residue using purified water and an inert gas.
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公开(公告)号：US11678547B2
公开(公告)日：2023-06-13
申请号：US17328026
申请日：2021-05-24
发明人： Kyungjin Jeon , Joonseok Park , Soyoung Koo , Myounghwa Kim , Eoksu Kim , Taesang Kim , Hyungjun Kim , Yeonkeon Moon , Geunchul Park , Sangwoo Sohn , Junhyung Lim , Hyelim Choi
CPC分类号： H01L27/3279 , H01L27/3248 , H01L27/3258 , H01L27/3265 , H01L51/524 , H01L51/5253 , H01L51/56 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1288 , H01L28/60 , H01L2227/323
摘要： A display device includes: a substrate; a first thin film transistor and a second thin film transistor arranged over the substrate; a display element connected to the first thin film transistor; a wiring connected to the second thin film transistor and including a first wiring layer and a second wiring layer; a pattern insulating layer arranged between the first wiring layer and the second wiring layer; a planarization layer covering the wiring; and a connection electrode arranged on the planarization layer and connected to the first wiring layer and the second wiring layer respectively through a first contact hole and a second contact hole.
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公开(公告)号：US20240324339A1
公开(公告)日：2024-09-26
申请号：US18429437
申请日：2024-02-01
发明人： Yunyong Nam , Soyoung Koo , Eoksu Kim , Hyungjun Kim
IPC分类号： H10K59/131 , G09G3/3233
CPC分类号： H10K59/131 , G09G3/3233 , G09G2300/0426 , G09G2300/0842
摘要： A display apparatus includes a substrate including a display area, in which a plurality of pixels are arranged, and a peripheral area outside the display area, a data line arranged in the display area and extending in a first direction, a first semiconductor pattern disposed on the data line and extending in a second direction crossing the first direction, a gate line disposed on the first semiconductor pattern and extending in the first direction to cross the first semiconductor pattern, and an anchor located at an end portion of the gate line and having a width greater than a width of the gate line.
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公开(公告)号：US11574987B2
公开(公告)日：2023-02-07
申请号：US17223505
申请日：2021-04-06
发明人： Kyungjin Jeon , Soyoung Koo , Eok Su Kim , Hyungjun Kim , Yunyong Nam , Jun Hyung Lim
IPC分类号： H01L27/32
摘要： An electronic apparatus includes a first transistor including a first oxide semiconductor pattern, a second transistor including a second oxide semiconductor pattern, a blocking layer including a conductive material, a signal line including a first line and a second line which are disposed on different layers, and a bridge pattern electrically connected to each of the first transistor, the first line of the signal line, and the second line of the signal line, wherein the first line of the signal line and the blocking layer are disposed on a same layer, and the second line of the signal line and the first oxide semiconductor pattern are disposed on a same layer.
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8.发明授权公开(公告)号：US11532687B2
公开(公告)日：2022-12-20
申请号：US16880792
申请日：2020-05-21
发明人： Sangwoo Sohn , Myounghwa Kim , TaeSang Kim , Hyungjun Kim , Yeon Keon Moon , Joon Seok Park , Sangwon Shin , Jun Hyung Lim , Hyelim Choi
IPC分类号： H01L27/32 , H01L51/56 , H01L51/52 , H01L29/786
摘要： A display panel includes a base layer, a first thin film transistor on the base layer, a second thin film transistor electrically coupled to the first thin film transistor, and a light emitting element electrically coupled to the second thin film transistor. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern on the first semiconductor pattern and including a gallium (Ga) oxide and a zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern. Accordingly, a signal transmission speed of the display panel may be improved, and electrical characteristics and reliability of the thin film transistor included in the display panel may be improved.
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公开(公告)号：US20190006450A1
公开(公告)日：2019-01-03
申请号：US15834628
申请日：2017-12-07
发明人： Sunhee Lee , Hyungjun Kim , Jun Hyung Lim , Whangje Woo
摘要： A method of manufacturing a semiconductor element is provided as follows. A semiconductor layer that has a two-dimensional layered structure is formed on a substrate having a source region, a drain region, and a channel region. A high-k insulating layer is formed on the semiconductor layer by atomic layer deposition using trimethyl aluminum as a precursor and isopropyl alcohol as a reactant gas. A gate electrode is formed in the channel region on the high-k insulating layer. An insulating interlayer is formed on the gate electrode. Source and drain electrodes are formed in the source and drain regions on the insulating interlayer.
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公开(公告)号：US11812647B2
公开(公告)日：2023-11-07
申请号：US17841206
申请日：2022-06-15
发明人： Soyoung Koo , Eoksu Kim , Hyungjun Kim , Yunyong Nam , Junhyung Lim , Kyungjin Jeon
IPC分类号： H10K59/131 , G09G3/3266 , G09G3/3291 , H10K59/122 , H10K59/12
CPC分类号： H10K59/131 , G09G3/3266 , G09G3/3291 , H10K59/122 , G09G2300/0426 , H10K59/1201
摘要： A display apparatus is disclosed that includes contact holes formed to expose at least a portion of a conductive layer or a semiconductor layer without damage to the surface of the conductive layer or the semiconductor layer, and a method of manufacturing the display apparatus. The display apparatus includes a substrate, a conductive mound arranged on the substrate, a first insulating mound arranged on the substrate, and a semiconductor layer including a first region arranged on the conductive mound, and a second region arranged on the first insulating mound. The second region of the semiconductor layer substantially covers an upper surface of the first insulating mound.
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