公开(公告)号：US08990549B2

公开(公告)日：2015-03-24

申请号：US13547045

申请日：2012-07-12

申请人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

发明人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

IPC分类号： G06F9/44

CPC分类号： G06F9/4408

摘要： A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

摘要翻译： 用于从NAND闪速存储器引导电子设备的方法和系统包括NAND闪存控制器，其接收用于获取存储在NAND闪速存储器中的预引导代码的事件触发。 基于事件触发类型，引导参数被加载到控制器中，包括NAND闪存的引导频率。 控制器通过检查存储器块的第一和第二或第一页和最后一页来搜索存储预引导代码的良好存储器块，并且基于事件触发类型获取部分或整个预引导代码 在引导频率。

公开(公告)号：US20140019741A1

公开(公告)日：2014-01-16

申请号：US13547045

申请日：2012-07-12

申请人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

发明人： Hemant Nautiyal ,  Nitin Gera ,  Amit Rao ,  Prabhjot Singh

IPC分类号： G06F9/445

CPC分类号： G06F9/4408

摘要： A method and system for booting an electronic device from a NAND flash memory includes a NAND flash controller that receives an event trigger for fetching a pre-boot code stored in the NAND flash memory. Based on the event trigger type, booting parameters are loaded into the controller including a boot frequency of the NAND flash memory. The controller searches for a good memory block in which the pre-boot code is stored by checking the first and second or the first and last pages of a memory block and fetches a portion or the entire pre-boot code based on the event trigger type at the boot frequency.

摘要翻译： 用于从NAND闪速存储器引导电子设备的方法和系统包括NAND闪存控制器，其接收用于获取存储在NAND闪速存储器中的预引导代码的事件触发。 基于事件触发类型，引导参数被加载到控制器中，包括NAND闪存的引导频率。 控制器通过检查存储器块的第一和第二或第一页和最后一页来搜索存储预引导代码的良好存储器块，并且基于事件触发类型获取部分或整个预引导代码 在引导频率。

公开(公告)号：US20160110119A1

公开(公告)日：2016-04-21

申请号：US14515500

申请日：2014-10-15

申请人： Prabhjot Singh ,  Nitin Gera ,  Hemant Nautiyal

发明人： Prabhjot Singh ,  Nitin Gera ,  Hemant Nautiyal

IPC分类号： G06F3/06 ,  G06F13/16 ,  G06F13/28

CPC分类号： G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G06F13/1694 ,  G06F13/28 ,  G06F2206/1014

摘要： In a processing system, an integrated function controller (IFC) for one or more memory devices, including a NAND flash memory device, provides direct memory access (DMA) functionality for writing data to and reading data from the NAND flash memory device, thereby reducing the level of CPU intervention required to support such operations. In one implementation, the CPU stores in system memory a descriptor-based DMA operation sequence of NAND flash operations and then triggers the IFC to implement the descriptor sequence. The IFC sequentially fetches and implements individual stored descriptors without interrupting the CPU or requiring any real-time CPU intervention using, for example, a “repeat while busy” polling descriptor type. The IFC frees up the CPU to perform other system-level operations, thereby increasing the efficiency of the processing system.

摘要翻译： 在处理系统中，用于一个或多个存储器设备的集成功能控制器（IFC）包括NAND闪存器件，提供用于将数据写入NAND数据并从NAND闪存器件读取数据的直接存储器访问（DMA）功能，从而减少 支持此类操作所需的CPU干预级别。 在一个实现中，CPU在系统存储器中存储NAND闪存操作的基于描述符的DMA操作序列，然后触发IFC来实现描述符序列。 IFC在不中断CPU或者要求使用例如“重复同时繁忙”轮询描述符类型的任何实时CPU干预的情况下，顺序地获取和实现各个存储的描述符。 IFC释放CPU执行其他系统级操作，从而提高处理系统的效率。

公开(公告)号：US09355691B2

公开(公告)日：2016-05-31

申请号：US14318685

申请日：2014-06-29

申请人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

发明人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

IPC分类号： G06F13/00 ,  G11C7/10 ,  G06F13/16

CPC分类号： G11C7/1057 ,  G06F13/1689 ,  G11C7/1066

摘要： A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

摘要翻译： 系统提供存储器和存储器控制器之间的同步读取数据采样，存储器控制器包括异步FIFO缓冲器，并输出时钟和其他控制信号。 使用出站控制信号（例如，read_enable）来使用时钟边缘计数器对读取访问的开始进行时间戳。 通过计数FIFO弹出，基于read_enable信号的时间戳值加上典型访问延迟来限定输入读取数据。 系统执行正确的数据采样，而不管控制器和存储器之间的传播延迟。 该系统可以在具有同步通信系统的片上系统（SOC）设备中实现。

公开(公告)号：US20150380067A1

公开(公告)日：2015-12-31

申请号：US14318685

申请日：2014-06-29

申请人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

发明人： Prabhjot Singh ,  Hemant Nautiyal ,  Amit Rao

IPC分类号： G11C7/22 ,  G11C7/10

CPC分类号： G11C7/1057 ,  G06F13/1689 ,  G11C7/1066

摘要： A system provides synchronous read data sampling between a memory and a memory controller, which includes an asynchronous FIFO buffer and which outputs a clock and other control signals. An outbound control signal (e.g., read_enable) is used to time-stamp the beginning of a read access using a clock edge counter. The incoming read data is qualified based on the time-stamped value of the read_enable signal plus typical access latency by counting FIFO pops. The system performs correct data sampling irrespective of propagation delays between the controller and memory. The system may be implemented in a System on a Chip (SOC) device having a synchronous communication system.

摘要翻译： 系统提供存储器和存储器控制器之间的同步读取数据采样，存储器控制器包括异步FIFO缓冲器，并输出时钟和其他控制信号。 使用出站控制信号（例如，read_enable）来使用时钟边缘计数器对读取访问的开始进行时间戳。 通过计数FIFO弹出，基于read_enable信号的时间戳值加上典型访问延迟来限定输入读取数据。 系统执行正确的数据采样，而不管控制器和存储器之间的传播延迟。 该系统可以在具有同步通信系统的片上系统（SOC）设备中实现。

公开(公告)号：US20120239900A1

公开(公告)日：2012-09-20

申请号：US13050948

申请日：2011-03-18

申请人： Hemant Nautiyal ,  Dhruv Satsangi

发明人： Hemant Nautiyal ,  Dhruv Satsangi

IPC分类号： G06F12/00

CPC分类号： G06F13/1668 ,  Y02D10/14

摘要： A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.

摘要翻译： 用于配置与存储器设备通信的存储器控​​制器的系统和方法将对所选择的引脚进行多路复用以进行数据传输。 存储器控制器包括一组引脚，其中该组的每个引脚与数据位和地址位相关联。 可编程逻辑块连接到该组引脚，并且使用该组引脚的子集来实现存储器件与存储器控制器之间的数据传输，这取决于存储器件的尺寸，使得不包括在该子集中的引脚是 可用于其他应用程序。

公开(公告)号：US08321649B2

公开(公告)日：2012-11-27

申请号：US13050948

申请日：2011-03-18

申请人： Hemant Nautiyal ,  Dhruv Satsangi

发明人： Hemant Nautiyal ,  Dhruv Satsangi

IPC分类号： G06F12/02

CPC分类号： G06F13/1668 ,  Y02D10/14

摘要： A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications.

摘要翻译： 用于配置与存储器设备通信的存储器控​​制器的系统和方法将对所选择的引脚进行多路复用以进行数据传输。 存储器控制器包括一组引脚，其中该组的每个引脚与数据位和地址位相关联。 可编程逻辑块连接到该组引脚，并且使用该组引脚的子集来实现存储器件与存储器控制器之间的数据传输，这取决于存储器件的尺寸，使得不包括在该子集中的引脚是 可用于其他应用程序。

公开(公告)号：US08285908B2

公开(公告)日：2012-10-09

申请号：US12692645

申请日：2010-01-24

申请人： Amar Nath Deogharia ,  Hemant Nautiyal

发明人： Amar Nath Deogharia ,  Hemant Nautiyal

IPC分类号： G06F13/36

CPC分类号： G06F13/4059

摘要： A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses. A managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, is used to determine a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces.

摘要翻译： 一种用于连接无序总线和多个有序总线和总线桥的方法。 总线桥包括多个有序总线接口，其中每个有序总线接口耦合到有序总线。 流控制逻辑电路耦合到无序总线和多个有序总线接口。 流控制逻辑电路控制无序总线与每个有序总线接口之间的事务请求流。 流控制逻辑电路包括用于更新与事务请求相关联的依赖关系分辨率属性和数据就绪属性的更新电路，以及用于存储依赖性解析属性，数据就绪属性和事务请求所指定的事务请求的共享存储器单元 有序的巴士。 用于耦合到共享存储器单元和多个有序总线接口的管理电路用于基于与事务请求相关联的依赖性解析属性和数据就绪属性来确定每个事务请求的准备状态，并且用于管理出队 基于有序总线接口的可用性，对有序总线接口的就绪事务请求。