公开(公告)号：US5093920A

公开(公告)日：1992-03-03

申请号：US408459

申请日：1989-09-15

申请人： Prathima Agrawal ,  William J. Dally ,  Anjur S. Krishnakumar

发明人： Prathima Agrawal ,  William J. Dally ,  Anjur S. Krishnakumar

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： An arrangement for implementing graph operations, generally, and circuit simulations in particular employing a plurality of substantially identical high speed special purpose processing elements (PE) that are flexibly interconnected through a switch to form a cluster. In addition to the processing element (PE) being programmable, the interconnection switch permits dynamically altered routing of signals between the processing elements. The processing elements include a queue unit which permits high speed asynchronous communication between the elements. Additional advantage is attained with a hierarchical arrangement where a plurality of clusters are interconnected in an n-cube arrangement, and all of the clusters communicate with a host computer.

摘要翻译： 一般来说，用于实现图形操作以及电路模拟的装置，特别是采用多个基本上相同的高速专用处理元件（PE），该高速专用处理元件（PE）通过开关灵活互连以形成一个集群。 除了可编程的处理元件（PE）之外，互连开关允许在处理元件之间动态地改变信号的路由。 处理元件包括允许元件之间的高速异步通信的队列单元。 通过分层布置来实现额外的优点，其中多个簇以n立方体布置互连，并且所有簇与主计算机通信。

公开(公告)号：US08674768B2

公开(公告)日：2014-03-18

申请号：US13352221

申请日：2012-01-17

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03G3/10

CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

摘要： An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

摘要翻译： 集成电路接收器包括第一通道，其包括响应于第一模式中的第一增益控制值的放大器，以接收输入信号并产生具有转变速率的第一放大信号。 第一通道中的检测电路根据检测到的转换速率来检测第一放大信号中的转换。 所检测的转变速率基于第一增益控制值。 增益控制逻辑基于期望的检测到的转变速率来调整第一增益控制值。 增益控制逻辑产生在第二模式期间使用的第二增益控制值。 第二增益控制值基于第一增益控制值。

公开(公告)号：US08555035B1

公开(公告)日：2013-10-08

申请号：US12831953

申请日：2010-07-07

申请人： Anjul Patney ,  William J. Dally

发明人： Anjul Patney ,  William J. Dally

IPC分类号： G06F9/44

CPC分类号： G06F8/441

摘要： One embodiment of the present invention sets forth a technique for using a multi-bank register file that reduces the size of or eliminates a switch and/or staging registers that are used to gather input operands for instructions. Each function unit input may be directly connected to one bank of the multi-bank register file with neither a switch nor a staging register. A compiler or register allocation unit ensures that the register file accesses for each instruction are conflict-free (no instruction can access the same bank more than once in the same cycle). The compiler or register allocation unit may also ensure that the register file accesses for each instruction are also aligned (each input of a function unit can only come from the bank connected to that input).

摘要翻译： 本发明的一个实施例提出了一种使用减少用于收集用于指令的输入操作数的开关和/或分段寄存器的大小或消除的多存储体寄存器堆的技术。 每个功能单元输入可以直接连接到多存储区寄存器文件的一行，既不带有开关也不是暂存寄存器。 编译器或寄存器分配单元确保每个指令的寄存器文件访问是无冲突的（没有指令可以在同一周期内多次访问同一个存储体）。 编译器或寄存器分配单元还可以确保每个指令的寄存器文件访问也被对齐（功能单元的每个输入只能来自连接到该输入的存储体）。

公开(公告)号：US08487681B2

公开(公告)日：2013-07-16

申请号：US13033426

申请日：2011-02-23

申请人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

发明人： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  G E (Francis) Yang

IPC分类号： H03K3/356

CPC分类号： H03K3/36 ,  H03K3/012 ,  H03K3/356121

摘要： One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

公开(公告)号：US08259841B2

公开(公告)日：2012-09-04

申请号：US13027893

申请日：2011-02-15

申请人： William J. Dally

发明人： William J. Dally

IPC分类号： H04L27/04 ,  H04L25/03 ,  H04L27/00 ,  H03K5/156

CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

公开(公告)号：US08238470B2

公开(公告)日：2012-08-07

申请号：US13090507

申请日：2011-04-20

申请人： William J. Dally

发明人： William J. Dally

IPC分类号： H04L27/04 ,  H04L25/03 ,  H04L27/00 ,  H03K5/156

CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

公开(公告)号：US08228930B1

公开(公告)日：2012-07-24

申请号：US11445934

申请日：2006-06-02

申请人： John J. Kim ,  William J. Dally

发明人： John J. Kim ,  William J. Dally

IPC分类号： H04L12/56

CPC分类号： H04L12/56 ,  H04L49/25

摘要： Interconnection router arrangements are implemented using a variety of arrangements and methods. Using one such arrangement, an interconnection network router arrangement sends data units between a set of router inputs and a set of router outputs. The interconnection network router arrangement includes a sub-switch that is capable of selectively transferring a data unit from an array of sub-switch inputs to an array of sub-switch outputs. The sub-switch has a memory circuit for storing the data unit before the data unit is transferred to a sub-switch output and a memory circuit for storing the data unit after the data unit is transferred from the sub-switch inputs and before the data unit is sent to a router output.

摘要翻译： 互连路由器布置使用各种布置和方法来实现。 使用一种这样的布置，互连网络路由器布置在一组路由器输入和一组路由器输出之间发送数据单元。 互连网络路由器布置包括子交换机，其能够选择性地将数据单元从子开关输入阵列传送到子开关输出阵列。 子开关具有用于在将数据单元传送到副开关输出之前存储数据单元的存储电路和用于在数据单元从子开关输入传送之后并在数据之前存储数据单元的存储电路 单元发送到路由器输出。

公开(公告)号：US08102212B2

公开(公告)日：2012-01-24

申请号：US12840150

申请日：2010-07-20

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03G3/10

CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

摘要： An integrated circuit receiver includes a first channel comprising an amplifier responsive to a first gain control value in a first mode to receive an input signal and generate a first amplified signal having a transition rate. Detection circuitry in the first channel detects transitions in the first amplified signal in accordance with a detected transition rate. The detected transition rate is based on the first gain control value. Gain control logic adjusts the first gain control value based on a desired detected transition rate. The gain control logic generates a second gain control value for use during a second mode. The second gain control value being based on the first gain control value.

摘要翻译： 集成电路接收器包括第一通道，其包括响应于第一模式中的第一增益控制值的放大器，以接收输入信号并产生具有转变速率的第一放大信号。 第一通道中的检测电路根据检测到的转换速率来检测第一放大信号中的转换。 所检测的转变速率基于第一增益控制值。 增益控制逻辑基于期望的检测到的转变速率来调整第一增益控制值。 增益控制逻辑产生在第二模式期间使用的第二增益控制值。 第二增益控制值基于第一增益控制值。

公开(公告)号：US07715494B2

公开(公告)日：2010-05-11

申请号：US11514637

申请日：2006-08-31

申请人： William J. Dally

发明人： William J. Dally

IPC分类号： H04L25/03

CPC分类号： H04L25/03019 ,  H04B1/0483 ,  H04B1/1081 ,  H04B1/16 ,  H04B3/04 ,  H04L1/0042 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/03025 ,  H04L25/03343 ,  H04L25/03878 ,  H04L25/03885 ,  H04L27/01

摘要： An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

摘要翻译： 提供在数字发射机中的均衡器补偿信号到数字接收机的信号衰减。 均衡器产生信号电平作为位历史的逻辑功能，以强调相对于重复信号电平的转换信号电平。 优选的均衡器包括使用查找表的FIR转换滤波器。 包括FIR滤波器和数模转换器的并行电路为低速电路提供高速均衡器。 均衡器特别适用于柜内和局域网传输，其中反馈电路有助于均衡器的自适应训练。

公开(公告)号：US20090292855A1

公开(公告)日：2009-11-26

申请号：US12352443

申请日：2009-01-12

申请人： Steven L. Scott ,  Dennis C. Abts ,  William J. Dally

发明人： Steven L. Scott ,  Dennis C. Abts ,  William J. Dally

IPC分类号： G06F13/20

CPC分类号： H04L45/7453 ,  G06F15/17362 ,  H04L45/00 ,  H04L45/28 ,  H04L45/566 ,  H04L45/745 ,  H04L49/15

摘要： A high-radix interprocessor communications system and method having a plurality of processor nodes, a plurality of first routers and a plurality of second routers. Each first router is connected to a processor node and to two or more second routers. Each first router includes input ports, output ports, row busses, columns channels and a plurality of subswitches arranged in a n×p matrix. Each row bus receives data from one of the plurality of input ports and distributes the data to two or more of the plurality of subswitches. Each column distributes data from one or more subswitches to one or more output ports. Each row bus includes a route selector, wherein the route selector includes a routing table which selects an output port for each packet and which routes the packet through one of the row busses to the selected output port.

摘要翻译： 具有多个处理器节点，多个第一路由器和多个第二路由器的高基数处理器通信系统和方法。 每个第一路由器连接到处理器节点和两个或更多个第二路由器。 每个第一路由器包括输入端口，输出端口，行总线，列通道和以n×p矩阵排列的多个子开关。 每行总线从多个输入端口之一接收数据，并将数据分配给多个子开关中的两个或多个。 每列将数据从一个或多个子交换分配到一个或多个输出端口。 每行行总线包括路由选择器，其中路由选择器包括路由选择表，该路由表选择每个分组的输出端口，并且通过一条行总线将分组路由到所选输出端口。