摘要:
Briefly, in accordance with one embodiment of the invention, a slot antenna may include a primary slot and one or more secondary slots. The size of the antenna may be reduced by adding one or more of the secondary slots which may add additional inductance to the antenna. Furthermore, the size of the antenna may be reduced by increasing the inductance of the secondary slots via increasing the length of the slots or by changing the shape of the slots. The antenna may include one or more MEMS varactors coupled to one or more of the secondary slots. The resonant frequency of the slot antenna may be tuned to a desired frequency by changing the capacitance value of one or more of the MEMS varactors to a desired capacitance value.
摘要:
An embodiment of the present invention provides an apparatus, comprising an oscillator capable of generating a clock signal, wherein said apparatus is capable of clock noise mitigation using a frequency adaptive algorithm, technique, process or system. And wherein said oscillator may be a voltage controlled oscillator (VCO) operating near a desired frequency used to generate an output signal. The clock noise mitigation may accomplished by portion of said VCO signal being fed into a first dividing circuit capable of dividing by a given number M, and a second dividing circuit, N, wherein said first and second dividing circuits may be capable of producing a signal close to the frequency of a reference oscillator, said VCO signal may then be compared via a phase comparator to a reference frequency and wherein the phase comparator signal may then be fed back to the VCO such that its frequency will “lock” to said reference oscillator. The M and N dividers may be set to enable the frequency increments to be as small as desired and may be dynamically programmable. Depending on the communication channels being used, the frequency of the clock may modified either up or down to avoid interference.
摘要:
An embodiment of the present invention provides an apparatus, comprising an oscillator capable of generating a clock signal, wherein said apparatus is capable of clock noise mitigation using a frequency adaptive algorithm, technique, process or system. And wherein said oscillator may be a voltage controlled oscillator (VCO) operating near a desired frequency used to generate an output signal. The clock noise mitigation may accomplished by portion of said VCO signal being fed into a first dividing circuit capable of dividing by a given number M, and a second dividing circuit, N, wherein said first and second dividing circuits may be capable of producing a signal close to the frequency of a reference oscillator, said VCO signal may then be compared via a phase comparator to a reference frequency and wherein the phase comparator signal may then be fed back to the VCO such that its frequency will “lock” to said reference oscillator. The M and N dividers may be set to enable the frequency increments to be as small as desired and may be dynamically programmable. Depending on the communication channels being used, the frequency of the clock may modified either up or down to avoid interference.
摘要:
Briefly, in accordance with one embodiment of the invention, a slot antenna may include a primary slot and one or more secondary slots. The size of the antenna may be reduced by adding one or more of the secondary slots which may add additional inductance to the antenna. Furthermore, the size of the antenna may be reduced by increasing the inductance of the secondary slots via increasing the length of the slots or by changing the shape of the slots. The antenna may include one or more MEMS varactors coupled to one or more of the secondary slots. The resonant frequency of the slot antenna may be tuned to a desired frequency by changing the capacitance value of one or more of the MEMS varactors to a desired capacitance value.