公开(公告)号：US07640522B2

公开(公告)日：2009-12-29

申请号：US11331605

申请日：2006-01-14

申请人： Puneet Gupta ,  Andrew B. Kahng ,  Chul-Hong Park

发明人： Puneet Gupta ,  Andrew B. Kahng ,  Chul-Hong Park

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G06F17/5068

摘要： A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their corresponding layout object perturbation distances. This leads to improved photolithographic characteristics such as reduced Critical Dimension (CD) errors and forbidden pitches in the standard-cell layout.

摘要翻译： 公开了一种用于在标准单元布局设计中详细布置布局对象的方法和系统。 布局对象包括单元格和蚀刻虚拟。 该方法包括基于编程的技术来计算布局对象的布局对象扰动距离。 该方法包括使用其对应的布局对象扰动距离调整布局对象。 这导致改进的光刻特性，例如在标准单元布局中减少临界尺寸（CD）误差和禁止间距。

公开(公告)号：US07945870B2

公开(公告)日：2011-05-17

申请号：US11725396

申请日：2007-03-19

申请人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

发明人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots.

摘要翻译： 用于在电路布局中检测热点的方法包括构建具有来自电路布局的节点，拐角边缘和邻近边缘的布局图，将布局图转换为相应的双图，并迭代地选择具有大于预定阈值的权重的边和节点 在每个迭代作为热点。

公开(公告)号：US07873929B2

公开(公告)日：2011-01-18

申请号：US11893096

申请日：2007-08-14

申请人： Andrew B. Kahng ,  Chul-Hong Park

发明人： Andrew B. Kahng ,  Chul-Hong Park

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of cells containing auxiliary patterns while improving an objective function of a resulting placement solution for the plurality of standard cells.

摘要翻译： 用于设计集成电路的方法和装置。 对于在栅极层上并入辅助图案的至少一个标准单元产生新的布局，以促进基于单元的光学邻近校正。 针对多个标准单元修改原始放置解决方案，以允许并入含有辅助图案的单元，同时改善针对多个标准单元的结果放置溶液的目标函数。

公开(公告)号：US20080235645A1

公开(公告)日：2008-09-25

申请号：US11725396

申请日：2007-03-19

申请人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

发明人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots.

摘要翻译： 用于在电路布局中检测热点的方法包括构建具有来自电路布局的节点，拐角边缘和邻近边缘的布局图，将布局图转换为相应的双图，并迭代地选择具有大于预定阈值的权重的边和节点 在每个迭代作为热点。

公开(公告)号：US08949768B2

公开(公告)日：2015-02-03

申请号：US13620669

申请日：2012-09-14

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

摘要翻译： 公开了一种标准细胞库。 标准单元库包含其中注释至少一个单元中的至少一个晶体管用于栅长度偏置的单元。 栅极长度偏置包括栅极长度的修改，以便改变修改的栅极长度的速度或功率消耗。 标准单元库是用于制造半导体器件（例如，作为半导体芯片的结果）的方法，通过制造在几何形状的一个或多个布局上限定的特征。 注释用于在使用用于制造半导体器件的几何形状之前识别哪些晶体管栅极特征将被修改。

公开(公告)号：US08490043B2

公开(公告)日：2013-07-16

申请号：US12717887

申请日：2010-03-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

公开(公告)号：US20130014073A1

公开(公告)日：2013-01-10

申请号：US13620690

申请日：2012-09-14

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5063 ,  G06F17/5068 ,  G06F2217/78

摘要： A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

公开(公告)号：US07865856B1

公开(公告)日：2011-01-04

申请号：US12075654

申请日：2008-03-12

申请人： Andrew B. Kahng ,  Puneet Gupta ,  Saumil Shah

发明人： Andrew B. Kahng ,  Puneet Gupta ,  Saumil Shah

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G06F17/5031 ,  G06F17/5036

摘要： A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.

摘要翻译： 使用静态性能分析器的方法，该静态性能分析器接受小区级网表的输入，对由晶体管级网表表示的电路执行静态性能分析。 该方法开始于通过用单元模型建模单个晶体管来将所述晶体管级网表转换为单元级网表。 然后，使用静态性能分析器来执行所述小区级网表的静态性能分析。 可以分析的性能特征是定时（静态时序分析）和泄漏功率。 所描述的方法也可用于统计静态时序和功率分析。

公开(公告)号：US07823098B1

公开(公告)日：2010-10-26

申请号：US11590581

申请日：2006-10-31

申请人： Cho W. Moon ,  Puneet Gupta ,  Paul J. Donehue ,  Andrew B. Kahng

发明人： Cho W. Moon ,  Puneet Gupta ,  Paul J. Donehue ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method of designing a digital circuit is described, so that it is likely to pass a signoff time test. The method begins with the running of a basic static time test on a partially developed version of the digital circuit, next a signoff time test is run for the partially developed version of the digital system. The differences between the results of the basic static time test and the signoff time test are noted and the prospective basic static time test passing conditions are altered so that if a similar system passes the basic static time test with the altered passing conditions it will be more likely to pass the signoff time test. Then, the partially developed version of the digital system is altered to yield a second partially developed version and the first static time test is run, with the altered passing conditions on the second partially developed version.

摘要翻译： 描述了一种设计数字电路的方法，从而可能通过签发时间测试。 该方法开始于在数字电路的部分开发版本上运行基本静态时间测试，接下来对数字系统的部分开发版本进行签发时间测试。 注意基本静态时间测试和签发时间测试的结果之间的差异，并改变预期的基本静态时间测试通过条件，以便如果类似的系统通过基本的静态时间测试与改变的通过条件，将会更多 可能通过签退时间测试。 然后，数字系统的部分开发版本被改变以产生第二部分开发的版本，并且运行第一静态时间测试，在第二部分开发版本上改变了通过条件。

公开(公告)号：US07814456B2

公开(公告)日：2010-10-12

申请号：US11267686

申请日：2005-11-04

申请人： Puneet Gupta ,  Andrew B. Kahng

发明人： Puneet Gupta ,  Andrew B. Kahng

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70783 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post-planarization topography of the wafer layer.

摘要翻译： 本发明提供了一种用于在集成电路（IC）的制造期间改进掩模版增强计算的方法和系统。 通过并入后平面化地形估计，改进了掩模版增强计算。 模拟晶片层的平坦化处理以估计后平面化形貌。 然后基于晶片层的后平面化形貌进行RET计算，例如子分辨率辅助特征插入，光学邻近校正和相移。