公开(公告)号：US20150055514A1

公开(公告)日：2015-02-26

申请号：US14504026

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Gary J. Ballantyne

IPC: H04B1/52 ,  H04J11/00

CPC classification number: H04B1/525 ,  H04B1/0475 ,  H04J11/0023

Abstract: A transmitter circuit is described. The transmitter circuit includes a first local oscillator that generates a first frequency equal to a duplex frequency. The transmitter circuit also includes a second local oscillator that generates a second frequency equal to a receive frequency. The transmitter circuit further includes a first mixer that combines the first frequency with a first input signal. The transmitter circuit also includes a first feedback loop. The first feedback loop includes a second mixer that combines the second frequency with a transmit signal and a first filter and a first adder that combines an output of the first mixer with an output of the first filter. The transmitter circuit also includes a third local oscillator that generates a third frequency equal to the receive frequency. The transmitter circuit further includes a third mixer that combines the third frequency with an output of the first adder.

Abstract translation: 描述发射机电路。 发射机电路包括产生等于双工频率的第一频率的第一本地振荡器。 发射机电路还包括产生等于接收频率的第二频率的第二本地振荡器。 发射机电路还包括将第一频率与第一输入信号组合的第一混频器。 发射机电路还包括第一反馈环路。 第一反馈回路包括将第二频率与发射信号和第一滤波器组合的第二混频器和将第一混频器的输出与第一滤波器的输出组合的第一加法器。 发射机电路还包括产生等于接收频率的第三频率的第三本地振荡器。 发射机电路还包括将第三频率与第一加法器的输出组合的第三混频器。

公开(公告)号：US08531219B1

公开(公告)日：2013-09-10

申请号：US13866871

申请日：2013-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jeremy D. Dunworth ,  Gary J. Ballantyne ,  Bhushan S. Asuri ,  Jifeng Geng ,  Gurkanwal S. Sahota

IPC: H03L7/06

CPC classification number: H03L7/08 ,  H03L7/093

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract translation: 在锁相环（PLL）处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号，并且还基于该数据信号。 根据另外的实施例，公开了装置和计算机可读介质。

公开(公告)号：US20130229212A1

公开(公告)日：2013-09-05

申请号：US13866871

申请日：2013-04-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jeremy D. Dunworth ,  Gary J. Ballantyne ,  Bhushan S. Asuri ,  Jifeng Geng ,  Gurkanwal S. Sahota

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/093

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract translation: 在锁相环（PLL）处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号，并且还基于该数据信号。 根据另外的实施例，公开了装置和计算机可读介质。