DEVICES, SYSTEMS, AND METHODS IMPLEMENTING A FRONT END PARTITION OF A WIRELESS MODEM
    1.
    发明申请
    DEVICES, SYSTEMS, AND METHODS IMPLEMENTING A FRONT END PARTITION OF A WIRELESS MODEM 有权
    设备,系统和方法实现无线调制解调器的前端分割

    公开(公告)号:US20140269650A1

    公开(公告)日:2014-09-18

    申请号:US13831265

    申请日:2013-03-14

    CPC classification number: H04W84/12 H04B1/006 H04W88/06

    Abstract: This disclosure provides systems, methods, and apparatus for implementing a front-end partition of a wireless modems. In one embodiment, a wireless communication apparatus is provided. The wireless communication apparatus includes a wireless local area network modem including a first chip including a first portion of the wireless local area network modem configured to process signals and a second chip including a second portion of the wireless local area network modem. The wireless communication apparatus further includes a wide area network modem. The wireless communication apparatus further includes a combining circuit configured to combine the signals processed by the first portion and a transmission line configured to transmit the combined signals to the second chip and the wide area network modem. The wireless communication apparatus further includes a data modem including interference cancellation circuitry configured to cancel interference between the wireless local area network modem and the wide area network modem.

    Abstract translation: 本公开提供了用于实现无线调制解调器的前端分区的系统,方法和装置。 在一个实施例中,提供了一种无线通信装置。 无线通信装置包括无线局域网调制解调器,其包括第一芯片,其包括被配置为处理信号的无线局域网调制解调器的第一部分和包括无线局域网调制解调器的第二部分的第二芯片。 无线通信装置还包括广域网调制解调器。 无线通信装置还包括:组合电路,被配置为组合由第一部分处理的信号和被配置为将组合信号发送到第二芯片和广域网调制解调器的传输线。 无线通信装置还包括数据调制解调器,其包括被配置为消除无线局域网调制解调器和广域网调制解调器之间的干扰的干扰消除电路。

    Devices, systems, and methods implementing a front end partition of a wireless modem

    公开(公告)号:US09907114B2

    公开(公告)日:2018-02-27

    申请号:US13831265

    申请日:2013-03-14

    CPC classification number: H04W84/12 H04B1/006 H04W88/06

    Abstract: This disclosure provides systems, methods, and apparatus for implementing a front-end partition of a wireless modems. In one embodiment, a wireless communication apparatus is provided. The wireless communication apparatus includes a wireless local area network modem including a first chip including a first portion of the wireless local area network modem configured to process signals and a second chip including a second portion of the wireless local area network modem. The wireless communication apparatus further includes a wide area network modem. The wireless communication apparatus further includes a combining circuit configured to combine the signals processed by the first portion and a transmission line configured to transmit the combined signals to the second chip and the wide area network modem. The wireless communication apparatus further includes a data modem including interference cancellation circuitry configured to cancel interference between the wireless local area network modem and the wide area network modem.

    Phase locked loop with digital compensation for analog integration
    3.
    发明授权
    Phase locked loop with digital compensation for analog integration 有权
    具有数字补偿的锁相环,用于模拟集成

    公开(公告)号:US08531219B1

    公开(公告)日:2013-09-10

    申请号:US13866871

    申请日:2013-04-19

    CPC classification number: H03L7/08 H03L7/093

    Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

    Abstract translation: 在锁相环(PLL)处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号,并且还基于该数据信号。 根据另外的实施例,公开了装置和计算机可读介质。

    PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION
    4.
    发明申请
    PHASE LOCKED LOOP WITH DIGITAL COMPENSATION FOR ANALOG INTEGRATION 有权
    用于模拟集成的数字补偿的相位锁定环

    公开(公告)号:US20130229212A1

    公开(公告)日:2013-09-05

    申请号:US13866871

    申请日:2013-04-19

    CPC classification number: H03L7/08 H03L7/093

    Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

    Abstract translation: 在锁相环(PLL)处执行数据信号的调制的方法包括至少部分地基于数据信号在PLL的高频端口生成数字环路信号。 该方法还包括区分数字环路信号以产生数字输入信号并将数字输入信号转换为模拟电流信号。 基于模拟电流信号产生第一反馈信号。 该方法还包括在PLL的较低频率端口处产生基于第一反馈信号的第二反馈信号,并且还基于该数据信号。 根据另外的实施例,公开了装置和计算机可读介质。

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