公开(公告)号：US09455716B2

公开(公告)日：2016-09-27

申请号：US14488248

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Hung-Chuan Pai ,  Gang Zhang

IPC: H03K21/02 ,  H04B1/40 ,  H03K5/133 ,  H03L7/081 ,  H03L7/16 ,  H03K23/66 ,  H03K5/00 ,  H03K5/13

CPC classification number: H03K21/02 ,  H03K5/00006 ,  H03K5/133 ,  H03K23/667 ,  H03L7/081 ,  H03L7/16 ,  H04B1/40

Abstract: Aspects of a reconfigurable frequency divider circuit are provided. A reconfigurable frequency divider can include a frequency divider that is configured to receive an input signal. The frequency divider can also include a delay circuit that is configured to receive a divided signal produced by the frequency divider. The frequency divider can also include a frequency multiplier that is configured to produce an output signal based on the delayed signal produced by the delay circuit, wherein the delay circuit is configured to receive the output signal.

Abstract translation: 提供可重构分频器电路的方面。 可重配置分频器可以包括被配置为接收输入信号的分频器。 分频器还可以包括被配置为接收由分频器产生的分频信号的延迟电路。 分频器还可以包括被配置为基于由延迟电路产生的延迟信号产生输出信号的倍频器，其中延迟电路被配置为接收输出信号。

公开(公告)号：US11336288B1

公开(公告)日：2022-05-17

申请号：US17315337

申请日：2021-05-09

Applicant: Qualcomm Incorporated

Inventor： Hung-Chuan Pai ,  Marco Zanuso

IPC: H03L7/089 ,  H03L7/093

Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.

公开(公告)号：US20180367135A1

公开(公告)日：2018-12-20

申请号：US15624744

申请日：2017-06-16

Applicant: QUALCOMM INCORPORATED

Inventor： Hung-Chuan Pai ,  Tsai-Pi Hung

IPC: H03K17/16 ,  H03B5/12

Abstract: A switched capacitance circuit selectively provides a capacitance across first and second output nodes in response to a selection control signal. The switched capacitance circuit may include a first capacitor coupled between the first output node and a mid-node, a second capacitor coupled between the second output node and the mid-node, and a switching circuit. The switching circuit is configured to switch the first and second capacitors in response to the selection control signal and to provide a bias voltage at the mid-node in response to the selection control signal.