-
公开(公告)号:US10482289B2
公开(公告)日:2019-11-19
申请号:US15685795
申请日:2017-08-24
Applicant: QUALCOMM Incorporated
Inventor: David Barr , Dafna Shaool , Rahul Gulati , Pranjal Bhuyan
Abstract: A computing device includes a hardware resource, a component to send a transaction signal including a target address of the hardware resource, a security data associated with an initiator of the transaction signal, and a safety data associated with the initiator, and an access control unit coupled to the component and the hardware resource, the access control unit to receive the transaction signal, determine whether security access is granted based on the transaction signal, determine whether safety access is granted based on the transaction signal, and allow access to the hardware resource based on both the security access and the safety access being granted.
-
公开(公告)号:US10481202B2
公开(公告)日:2019-11-19
申请号:US15835227
申请日:2017-12-07
Applicant: QUALCOMM Incorporated
Inventor: Arvind Jain , Nishi Bhushan Singh , Rahul Gulati , Pranjal Bhuyan , Rakesh Kumar Kinger , Roberto Averbuj
IPC: G01R31/317 , G01R31/3187 , G01R31/319 , G01R31/3183 , G01R31/3185 , G06F9/448
Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.
-
公开(公告)号:US10389379B2
公开(公告)日:2019-08-20
申请号:US15594322
申请日:2017-05-12
Applicant: QUALCOMM Incorporated
Inventor: Rahul Gulati , Palkesh Jain , Pranjal Bhuyan , Mohammad Reza Kakoee
Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.
-
公开(公告)号:US10061644B2
公开(公告)日:2018-08-28
申请号:US14994078
申请日:2016-01-12
Applicant: QUALCOMM INCORPORATED
Inventor: Nhon Quach , Mainak Biswas , Pranjal Bhuyan , Jeffrey Shabel , Robert Hardacker , Rahul Gulati , Mattheus Heddes
IPC: G06F12/00 , G11C29/52 , G06F11/10 , G06F12/0888 , G06F12/08
CPC classification number: G06F11/1064 , G06F11/1012 , G06F12/08 , G06F12/0888 , G06F2212/1032 , G06F2212/1044 , G06F2212/1056 , G06F2212/281 , G06F2212/401 , G06F2212/466
Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
-
公开(公告)号:US20170222430A1
公开(公告)日:2017-08-03
申请号:US15012723
申请日:2016-02-01
Applicant: QUALCOMM Incorporated
Inventor: Virendra Bansal , Rahul Gulati , Pranjal Bhuyan , Palkesh Jain
CPC classification number: H02H9/02 , G01R31/025 , G01R31/2853 , H01L23/62
Abstract: An integrated circuit (IC) is disclosed herein for short-resistant output pin circuitry. In an example aspect, an integrated circuit includes a short-resistant pin and an adjacent pin. The integrated circuit also includes a short-resistant pad that is coupled to the short-resistant pin and an adjacent pad that is coupled to the adjacent pin. The integrated circuit further includes short-resistant circuitry that is coupled to the short-resistant pad and the adjacent pad. The short-resistant circuitry is implemented to detect a short-circuit condition between the short-resistant pin and the adjacent pin and to reduce an effect of the short-circuit condition on the short-resistant pin.
-
公开(公告)号:US20170094268A1
公开(公告)日:2017-03-30
申请号:US14864348
申请日:2015-09-24
Applicant: QUALCOMM Incorporated
Inventor: Rahul Gulati , John Chi Kit Wong , Pranjal Bhuyan , Sanjay Gupta , Hemang Jayant Shah
CPC classification number: H04N17/004 , B60K35/00 , G09G3/006
Abstract: A display processor of a display system may receive an image that includes a test pattern. An input checksum may be associated with the test pattern. Hardware units of the display processor may process the image. The display system may generate an output checksum based at least in part on the test pattern after processing of the image. The display system may detect a fault in the hardware units of the display processor based on determining a difference between the input checksum and the output checksum.
-
公开(公告)号:US20190018408A1
公开(公告)日:2019-01-17
申请号:US15648347
申请日:2017-07-12
Applicant: QUALCOMM Incorporated
Inventor: Rahul Gulati , Mainak Biswas , Pranjal Bhuyan , Anshuman Saxena
IPC: G05D1/00 , G05D1/02 , G08G1/0962 , G08G1/0968 , G07C5/00
Abstract: Devices and methods are disclosed for verifying the integrity of a sensing system. In one aspect, a vehicle includes an integrated circuit configured to support a message-based protocol between the integrated circuit and a sensor device associated with the vehicle, and send a sensor capability safety support message, as part of the message-based protocol, to determine one or more capabilities of the sensor device. The integrated circuit is also configured to receive, in response to the sensor capability safety support message, identification data corresponding to the sensor device, from the sensor device. The memory is configured to store a plurality of request data corresponding to a plurality of fields supported by the message-based protocol and associated with the integrated circuit and the sensor device capabilities, and store the response, including the identification data, from the sensor device.
-
公开(公告)号:US09955150B2
公开(公告)日:2018-04-24
申请号:US14864348
申请日:2015-09-24
Applicant: QUALCOMM Incorporated
Inventor: Rahul Gulati , John Chi Kit Wong , Pranjal Bhuyan , Sanjay Gupta , Hemang Jayant Shah
CPC classification number: H04N17/004 , B60K35/00 , G09G3/006
Abstract: A display processor of a display system may receive an image that includes a test pattern. An input checksum may be associated with the test pattern. Hardware units of the display processor may process the image. The display system may generate an output checksum based at least in part on the test pattern after processing of the image. The display system may detect a fault in the hardware units of the display processor based on determining a difference between the input checksum and the output checksum.
-
公开(公告)号:US20170123897A1
公开(公告)日:2017-05-04
申请号:US14994078
申请日:2016-01-12
Applicant: QUALCOMM INCORPORATED
Inventor: Nhon Quach , Mainak Biswas , Pranjal Bhuyan , Jeffrey Shabel , Robert Hardacker , Rahul Gulati , Mattheus Heddes
CPC classification number: G06F11/1064 , G06F11/1012 , G06F12/08 , G06F12/0888 , G06F2212/1032 , G06F2212/1044 , G06F2212/1056 , G06F2212/281 , G06F2212/401 , G06F2212/466
Abstract: Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.
-
-
-
-
-
-
-
-