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    Computing device to provide access control to a hardware resource
    1.
    发明授权
    Computing device to provide access control to a hardware resource 有权

    公开(公告)号：US10482289B2

    公开(公告)日：2019-11-19

    申请号：US15685795

    申请日：2017-08-24

    Applicant: QUALCOMM Incorporated

    Inventor： David Barr ,  Dafna Shaool ,  Rahul Gulati ,  Pranjal Bhuyan

    IPC: G06F21/00 ,  G06F21/70 ,  G06F21/50 ,  G06F21/62 ,  G06F9/50

    Abstract: A computing device includes a hardware resource, a component to send a transaction signal including a target address of the hardware resource, a security data associated with an initiator of the transaction signal, and a safety data associated with the initiator, and an access control unit coupled to the component and the hardware resource, the access control unit to receive the transaction signal, determine whether security access is granted based on the transaction signal, determine whether safety access is granted based on the transaction signal, and allow access to the hardware resource based on both the security access and the safety access being granted.

    Error correcting code testing
    3.
    发明授权
    Error correcting code testing 有权

    公开(公告)号：US10389379B2

    公开(公告)日：2019-08-20

    申请号：US15594322

    申请日：2017-05-12

    Applicant: QUALCOMM Incorporated

    Inventor： Rahul Gulati ,  Palkesh Jain ,  Pranjal Bhuyan ,  Mohammad Reza Kakoee

    IPC: H03M13/01 ,  H03M13/00 ,  G06F11/22

    Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

    SHORT-RESISTANT OUTPUT PIN CIRCUITRY
    5.
    发明申请
    SHORT-RESISTANT OUTPUT PIN CIRCUITRY 审中-公开

    公开(公告)号：US20170222430A1

    公开(公告)日：2017-08-03

    申请号：US15012723

    申请日：2016-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Virendra Bansal ,  Rahul Gulati ,  Pranjal Bhuyan ,  Palkesh Jain

    IPC: H02H9/02 ,  H01L23/62 ,  G01R31/02

    CPC classification number: H02H9/02 ,  G01R31/025 ,  G01R31/2853 ,  H01L23/62

    Abstract: An integrated circuit (IC) is disclosed herein for short-resistant output pin circuitry. In an example aspect, an integrated circuit includes a short-resistant pin and an adjacent pin. The integrated circuit also includes a short-resistant pad that is coupled to the short-resistant pin and an adjacent pad that is coupled to the adjacent pin. The integrated circuit further includes short-resistant circuitry that is coupled to the short-resistant pad and the adjacent pad. The short-resistant circuitry is implemented to detect a short-circuit condition between the short-resistant pin and the adjacent pin and to reduce an effect of the short-circuit condition on the short-resistant pin.

    SYSTEMS AND METHODS FOR VERIFYING INTEGRITY OF A SENSING SYSTEM
    7.
    发明申请
    SYSTEMS AND METHODS FOR VERIFYING INTEGRITY OF A SENSING SYSTEM 审中-公开

    公开(公告)号：US20190018408A1

    公开(公告)日：2019-01-17

    申请号：US15648347

    申请日：2017-07-12

    Applicant: QUALCOMM Incorporated

    Inventor： Rahul Gulati ,  Mainak Biswas ,  Pranjal Bhuyan ,  Anshuman Saxena

    IPC: G05D1/00 ,  G05D1/02 ,  G08G1/0962 ,  G08G1/0968 ,  G07C5/00

    Abstract: Devices and methods are disclosed for verifying the integrity of a sensing system. In one aspect, a vehicle includes an integrated circuit configured to support a message-based protocol between the integrated circuit and a sensor device associated with the vehicle, and send a sensor capability safety support message, as part of the message-based protocol, to determine one or more capabilities of the sensor device. The integrated circuit is also configured to receive, in response to the sensor capability safety support message, identification data corresponding to the sensor device, from the sensor device. The memory is configured to store a plurality of request data corresponding to a plurality of fields supported by the message-based protocol and associated with the integrated circuit and the sensor device capabilities, and store the response, including the identification data, from the sensor device.

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