公开(公告)号：US20240370369A1

公开(公告)日：2024-11-07

申请号：US18484950

申请日：2023-10-11

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Sparsh Singhai ,  Subbarao Palacharla ,  Simon Peter William Booth ,  Girish Bhat ,  Ling Feng Huang ,  Scott Cheng ,  Yen-Kuan Wu ,  Mohammad Tamjidi

IPC: G06F12/06 ,  G06F12/0873

Abstract: Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.

公开(公告)号：US11907138B2

公开(公告)日：2024-02-20

申请号：US17646690

申请日：2021-12-31

Applicant: QUALCOMM Incorporated

Inventor： Hiral Nandu ,  Subbarao Palacharla ,  George Patsilaras ,  Alain Artieri ,  Simon Peter William Booth ,  Vipul Gandhi ,  Girish Bhat ,  Yen-Kuan Wu ,  Younghoon Kim

IPC: G06F12/123 ,  G06F9/30

CPC classification number: G06F12/123 ,  G06F9/30101

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

公开(公告)号：US11803472B2

公开(公告)日：2023-10-31

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

CPC classification number: G06F12/084 ,  G06F1/3212 ,  G06F2212/62

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US09304844B2

公开(公告)日：2016-04-05

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/36 ,  G06F11/07

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。

公开(公告)号：US11783042B2

公开(公告)日：2023-10-10

申请号：US16903982

申请日：2020-06-17

Applicant: QUALCOMM INCORPORATED

Inventor： Steven Halter ,  Samar Asbe ,  Miguel Ballesteros ,  Girish Bhat ,  Mahadevamurty Nemani

IPC: G06F21/57 ,  G06F9/445 ,  G06F9/50 ,  G06F21/62

CPC classification number: G06F21/575 ,  G06F9/445 ,  G06F9/5016 ,  G06F21/572 ,  G06F21/62 ,  G06F2221/034

Abstract: Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

公开(公告)号：US20230029696A1

公开(公告)日：2023-02-02

申请号：US17390274

申请日：2021-07-30

Applicant: QUALCOMM Incorporated

Inventor： Girish Bhat ,  Subbarao Palacharla ,  Jeffrey Shabel ,  Isaac Berk ,  Kedar Bhole ,  Vipul Gandhi ,  George Patsilaras ,  Sparsh Singhai

IPC: G06F12/084 ,  G06F1/3212

Abstract: Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

公开(公告)号：US20140245076A1

公开(公告)日：2014-08-28

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/30

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。