公开(公告)号：US10141894B1

公开(公告)日：2018-11-27

申请号：US15640659

申请日：2017-07-03

Applicant: QUALCOMM INCORPORATED

Inventor： Karthikeya Aruppukottai Boominathan ,  Krishnaswamy Thiagarajan ,  Mahim Ranjan

IPC: H03F1/22 ,  H03F1/32 ,  H03F3/195

Abstract: A circuit includes a first amplifier path comprising a first amplifier, MA, a second amplifier path comprising a cascode device and a second amplifier, MB, a node defined by a source of the cascode device and a drain of the second amplifier, MB, and a capacitance coupled between the node and a source of the second amplifier, MB.

公开(公告)号：US10581389B1

公开(公告)日：2020-03-03

申请号：US16146525

申请日：2018-09-28

Applicant: QUALCOMM Incorporated

Inventor： Andreea Balteanu ,  Karthikeya Aruppukottai Boominathan ,  Mahim Ranjan ,  Ning Yuan

IPC: H03F3/45 ,  H03F1/56 ,  H04B1/16 ,  H03F1/02 ,  H04B1/04

Abstract: A reconfigurable amplifier load includes a power supply node, a first inductor comprising a first terminal coupled to a first switch, and a second inductor comprising a first terminal coupled to a second switch. The reconfigurable amplifier load further includes a third inductor comprising a first terminal coupled to the first switch. The first switch is configured to selectively couple the first terminal of the third inductor to the power supply node. A fourth inductor comprising a first terminal coupled to the second switch. The second switch is configured to selectively couple the first terminal of the fourth inductor to the power supply node. At least one additional switch configured to selectively couple a second terminal of the first inductor or a second terminal of the second inductor or both the second terminal of the first inductor and the second terminal of the second inductor to the power supply node.

公开(公告)号：US10164637B2

公开(公告)日：2018-12-25

申请号：US15441750

申请日：2017-02-24

Applicant: QUALCOMM Incorporated

Inventor： Sreenivasa Mallia ,  Ayush Mittal ,  Krishnaswamy Thiagarajan ,  Karthikeya Aruppukottai Boominathan

IPC: H03K19/0185

Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.