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公开(公告)号：US20190089358A1
公开(公告)日：2019-03-21
申请号：US15711708
申请日：2017-09-21
Applicant: Qualcomm Incorporated
CPC classification number: H03L7/07 , H03K5/133 , H03L7/0812 , H03L7/0814 , H03L7/0891 , H03L7/093 , H03L7/0995
Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.
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公开(公告)号：US10447280B2
公开(公告)日：2019-10-15
申请号：US15711708
申请日：2017-09-21
Applicant: Qualcomm Incorporated
Abstract: An integrated circuit is disclosed that implements a delay-locked loop with differential delay lines. In an example aspect, the integrated circuit includes a first delay line, a second delay line, and control circuitry. The first and second delay lines are coupled to a reference clock source to receive a reference clock. The first delay line produces a first delayed signal that is delayed relative to the reference clock by a first delay amount. The second delay line produces a second delayed signal that is delayed relative to the reference clock by a second delay amount. The control circuitry is coupled to the first and second delay lines. The control circuitry is configured to receive the first delayed signal, to receive the second delayed signal, and to adjust the first delay amount or the second delay amount based on the first delayed signal and the second delayed signal.
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公开(公告)号：US10348528B2
公开(公告)日：2019-07-09
申请号：US15472454
申请日：2017-03-29
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Bhushan Shanti Asuri , Krishnaswamy Thiagarajan , Sameer Vasantlal Vora , Mahim Ranjan
Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.
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公开(公告)号：US20180139078A1
公开(公告)日：2018-05-17
申请号：US15472454
申请日：2017-03-29
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Bhushan Shanti Asuri , Krishnaswamy Thiagarajan , Sameer Vasantlal Vora , Mahim Ranjan
IPC: H04L25/03
CPC classification number: H04L25/03 , H03D7/1458 , H03D7/165 , H03D2200/0082 , H03D2200/0086 , H03H7/21 , H03H2007/013 , H04B1/0475 , H04L25/03828 , H04L27/36
Abstract: A system includes: a baseband phase generator configured to receive differential in-phase (I) and quadrature (Q) signals and configured to output N phase-shifted baseband signals, wherein N is greater than 4, further wherein the baseband phase generator comprises a plurality of notch filters configured to receive the I and Q signals; and an upconverter configured to receive the phase-shifted baseband signals, to perform mixing on the phase-shifted baseband signals, and to output a differential upconverted signal.
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公开(公告)号：US09660585B2
公开(公告)日：2017-05-23
申请号：US14742351
申请日：2015-06-17
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Gireesh Rajendran , Rahul Karmaker
CPC classification number: H03F1/0205 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/3022 , H03F3/45192 , H03F3/45219 , H03F3/45654 , H03F2200/294 , H03F2200/451 , H03F2203/21106 , H03F2203/30015 , H03F2203/45008 , H03F2203/45134
Abstract: A class AB amplifier may include an input stage, a first folded cascode stage, a second folded cascode stage, and a class AB output stage. In some embodiments, the class AB output stage may provide differential output signals. The common-mode voltage of the differential output signals may be controlled via a correction signal coupled to a selected folded cascode stage. The correction signal may control the common-mode voltage of the differential output signals by altering bias currents within the selected folded cascode stage. The other cascode stage may include bias currents controlled by relatively fixed bias voltages.
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Patent Agency Ranking
公开(公告)号：US09160309B2
公开(公告)日：2015-10-13
申请号：US14103645
申请日：2013-12-11
Applicant: QUALCOMM Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Vinod Venugopal Panikkath , Ayush Mittal , Alok Joshi
CPC classification number: H03H11/1213 , G05F1/445 , H02M11/00 , H03H11/045 , H03H2011/0483
Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.
Abstract translation: 公开了一种区域有效的基带滤波器。 在一个示例性实施例中，一种装置包括电流 - 电压（I-V）滤波器，其被配置为在输入端口处接收输入电流信号，并且基于反馈跨导在输出端口处生成经滤波的输出电压信号。 除了信号电流之外，输入电流信号包括输入DC电流。 该装置还包括连接在输出端口和输入端口之间的反馈电路，反馈电路具有至少一个晶体管，其被配置为将输入的DC电流耦合到信号地，并为I-V滤波器提供反馈跨导。
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公开(公告)号：US10742244B1
公开(公告)日：2020-08-11
申请号：US16702366
申请日：2019-12-03
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Arnab Chakraborty , Krishnaswamy Thiagarajan
IPC: H04B1/04
Abstract: A device has a first switch in a first transmit path coupled between an output of a first DAC (digital-to-analog converter) in the first transmit path and an input of a first baseband filter in the first transmit path. The device also includes a second switch coupled between the output of the first DAC and an input of a second baseband filter in a second transmit path. The second switch is permanently open. The device also has a third switch and a fourth switch. The third switch is coupled between an output of a second DAC in the second transmit path and the input of the second baseband filter. The fourth switch is coupled between the output of the second DAC and the input of the first baseband filter.
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公开(公告)号：US10454509B2
公开(公告)日：2019-10-22
申请号：US15962865
申请日：2018-04-25
Applicant: QUALCOMM Incorporated
Inventor： Bhushan Shanti Asuri , Krishnaswamy Thiagarajan , Ashok Swaminathan , Shahin Mehdizad Taleie , Yen-Wei Chang , Vinod Panikkath , Sameer Vasantlal Vora , Ayush Mittal , Tonmoy Biswas , Sy-Chyuan Hwu , Zhilong Tang , Ibrahim Chamas , Ping Wing Lai , Behnam Sedighi , Dongwon Seo , Nitz Saputra
Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.
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公开(公告)号：US20150162895A1
公开(公告)日：2015-06-11
申请号：US14103645
申请日：2013-12-11
Applicant: QUALCOMM Incorporated
Inventor： Gireesh Rajendran , Rakesh Kumar , Vinod Venugopal Panikkath , Ayush Mittal , Alok Joshi
CPC classification number: H03H11/1213 , G05F1/445 , H02M11/00 , H03H11/045 , H03H2011/0483
Abstract: An area efficient baseband filter is disclosed. In an exemplary embodiment, an apparatus includes a current to voltage (I-V) filter configured to receive an input current signal at an input port and generate a filtered output voltage signal at an output port based on a feedback transconductance. The input current signal comprises an input DC current in addition to a signal current. The apparatus also includes a feedback circuit connected between the output port and the input port, the feedback circuit having at least one transistor configured to couple the input DC current to a signal ground and to provide the feedback transconductance for the I-V filter.
Abstract translation: 公开了一种区域有效的基带滤波器。 在一个示例性实施例中，一种装置包括电流 - 电压（I-V）滤波器，其被配置为在输入端口处接收输入电流信号，并且基于反馈跨导在输出端口处生成经滤波的输出电压信号。 除了信号电流之外，输入电流信号包括输入DC电流。 该装置还包括连接在输出端口和输入端口之间的反馈电路，反馈电路具有至少一个晶体管，其被配置为将输入的DC电流耦合到信号地，并为I-V滤波器提供反馈跨导。
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公开(公告)号：US11736071B2
公开(公告)日：2023-08-22
申请号：US17208864
申请日：2021-03-22
Applicant: QUALCOMM Incorporated
Inventor： Ayush Mittal , Sreenivasa Mallia , Arpit Gupta , Krishnaswamy Thiagarajan , Bhushan Shanti Asuri
CPC classification number: H03F1/42 , H03F3/245 , H03F2200/09 , H03F2200/36 , H03F2200/451
Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.
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