公开(公告)号：US09958918B2

公开(公告)日：2018-05-01

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US20170336845A1

公开(公告)日：2017-11-23

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20

CPC classification number: G06F1/28 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/78 ,  G06T1/20 ,  G06T2200/28 ,  H01L23/525 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11881

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US20170336840A1

公开(公告)日：2017-11-23

申请号：US15162452

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3206

Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.

公开(公告)号：US20140374873A1

公开(公告)日：2014-12-25

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L23/538 ,  G06F17/50

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US10394299B2

公开(公告)日：2019-08-27

申请号：US15162371

申请日：2016-05-23

Applicant: QUALCOMM Incorporated

Inventor： Satish Raj ,  Shiva Ram Chandrasekaran ,  Li Qiu ,  Arun Tyagi ,  Mathew Philip ,  Rajesh Verma

IPC: G06F1/28 ,  G06T1/20 ,  G06F17/50 ,  H01L23/525 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.

公开(公告)号：US09190358B2

公开(公告)日：2015-11-17

申请号：US14484904

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  H01L23/538 ,  G06F17/50 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US08853815B1

公开(公告)日：2014-10-07

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: H01L29/00 ,  H01L21/82 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.

Abstract translation: 本文提供了一种半导体装置，用于缓冲通过与第一功率域相关联的一个或多个区域路由的网络，所述第一功率域不同于与缓冲器和缓冲网络相关联的第二功率域，通过将这些缓冲器的位置限制在与 第二功率域。 这提供了缓冲网络的路由，其不仅将基于从点A到点B行进的最短距离而被确定，而且还考虑了半导体装置上的路由拥塞。 因此，如果半导体装置上的区域拥塞，则缓冲网可以围绕拥塞进行路由。 因此，尽管通过集成电路的特定信号所采取的路径不是直接路由，但是它仍然可以是支持特定信号需要传送的速度的距离。

公开(公告)号：US20140264715A1

公开(公告)日：2014-09-18

申请号：US13831360

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Sundararajan Ranganathan ,  Paras Gupta ,  Raghavendra Dasegowda ,  Rajesh Verma ,  Parissa Najdesamii

IPC: G06F17/50 ,  H01L29/06

CPC classification number: H01L23/538 ,  G06F17/5077 ,  G06F2217/78 ,  H01L27/0203 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.