公开(公告)号：US20240038831A1

公开(公告)日：2024-02-01

申请号：US17878758

申请日：2022-08-01

Applicant: QUALCOMM Incorporated

Inventor： Ryan LANE ,  Charles David PAYNTER ,  Durodami LISK ,  Darko POPOVIC ,  Yue LI ,  Shree Krishna PANDEY

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L24/16

Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

公开(公告)号：US20240425063A1

公开(公告)日：2024-12-26

申请号：US18338576

申请日：2023-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Vijayakumar Ashok DIBBAD ,  Jeffrey GEMAR ,  Shree Krishna PANDEY

IPC: B60W50/02 ,  B60W50/035 ,  B60W50/14

Abstract: Degradation of a power delivery network (PDN) in a computing device may be detected as part of a self-test during booting of the computing device or a device subsystem. The computing device may be an automotive vehicle control system. A clock signal provided to logic circuitry supplied by the PDN may be modulated, and the modulation frequency may be varied over a range. Voltage droop values in the logic circuitry may be measured in response to the modulation frequencies over the range. Impedance values may be determined by determining an odd harmonic of each of the voltage droop values. The impedance values may be compared with thresholds, and an alert or other indication may be issued if one or more of the impedance values exceeds a threshold.

公开(公告)号：US20230402380A1

公开(公告)日：2023-12-14

申请号：US17835861

申请日：2022-06-08

Applicant: QUALCOMM Incorporated

Inventor： Biancun XIE ,  Shree Krishna PANDEY

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/28 ,  H01L21/56 ,  H01L21/768 ,  H01L25/065

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/28 ,  H01L21/563 ,  H01L21/76895 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A package comprising a substrate, a bridge located in the substrate, a first integrated device coupled to the substrate and a second integrated device coupled to the substrate. The bridge includes a bridge substrate; at least one first bridge dielectric layer coupled to a first surface of the bridge substrate; at least one first bridge interconnect located in the at least one first bridge dielectric layer; at least one second bridge dielectric layer coupled to a second surface of the bridge substrate; at least one second bridge interconnect located in the at least one second bridge dielectric layer; and at least one bridge interconnect that extends through the at least one first bridge dielectric layer and the bridge substrate.

公开(公告)号：US20230005901A1

公开(公告)日：2023-01-05

申请号：US17364318

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Biancun XIE ,  Shree Krishna PANDEY

IPC: H01L25/18 ,  H01L27/01 ,  H01L49/02 ,  H01L25/00

Abstract: A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

公开(公告)号：US20220344249A1

公开(公告)日：2022-10-27

申请号：US17242083

申请日：2021-04-27

Applicant: QUALCOMM Incorporated

Inventor： Biancun XIE ,  Shree Krishna PANDEY ,  Irfan KHAN ,  Miguel MIRANDA CORBALAN ,  Stanley Seungchul SONG

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.