公开(公告)号：US10482016B2

公开(公告)日：2019-11-19

申请号：US15684418

申请日：2017-08-23

Applicant: QUALCOMM Incorporated

Inventor： Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.

公开(公告)号：US20190073323A1

公开(公告)日：2019-03-07

申请号：US15698386

申请日：2017-09-07

Applicant: QUALCOMM INCORPORATED

Inventor： Siddesh Halavarthi Math Revana ,  Kaustav Roychowdhury

IPC: G06F13/16 ,  G06F13/40 ,  G06F12/0804

Abstract: Categories of transaction requests from a processor may be buffered until one or more conditions occur, rather than being immediately transferred to a bus interconnect system. Transaction request traffic between the processor and bus interconnect system may be monitored, and it may be determined whether a transaction request is of a first category rather than a second category. First-category bus transaction requests are stored in a buffer. Transaction request traffic between the bus interconnect system and one or more client components may also be monitored. It may be determined whether an aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than a threshold. If the aggregate amount of the transaction request traffic between the bus interconnect system and the client components is lower than the threshold, buffered bus transaction requests may be transferred to the bus interconnect system.

公开(公告)号：US20200285584A1

公开(公告)日：2020-09-10

申请号：US16292178

申请日：2019-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana ,  Srivatsa Vaddagiri ,  Satyaki Mukherjee

IPC: G06F12/0891 ,  G06F12/0837 ,  G06F12/0842 ,  G06F12/0897

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.

公开(公告)号：US20190324932A1

公开(公告)日：2019-10-24

申请号：US15958438

申请日：2018-04-20

Applicant: QUALCOMM Incorporated

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana

IPC: G06F13/24 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F12/084 ,  G06F11/34 ,  G06F11/30

Abstract: Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.

公开(公告)号：US20190065372A1

公开(公告)日：2019-02-28

申请号：US15684418

申请日：2017-08-23

Applicant: QUALCOMM Incorporated

Inventor： Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F1/3287 ,  G06F12/0811 ,  G06F12/084 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/621

Abstract: Providing private cache allocation for power-collapsed processor cores in processor-based systems is provided. In one aspect, a processor-based system provides multiple processor cores, each residing within its own processor core power domain. Each processor core is provided with a private cache residing within its own private cache power domain, configured to be power-controlled independently of the corresponding processor core power domain. When a first processor core is placed in a power-collapsed state, a snoop controller corresponding to the private cache of the first processor core maintains power to the private cache power domain of the private cache, allowing the private cache to remain online. The snoop controller also enables allocation and snooping of the private cache by a second processor core while the first processor core remains in the power-collapsed state. In this manner, each private cache may be used for data-caching operations while its corresponding processor core is power-collapsed.