公开(公告)号：US20150286270A1

公开(公告)日：2015-10-08

申请号：US14291100

申请日：2014-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： Sreekumar Padmanabhan ,  Satyaki Mukherjee

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F1/3275 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F2212/6026 ,  G06F2212/654 ,  Y02D10/13 ,  Y02D10/14

Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR (double-data rate) memory, that corresponds with the magnitude of the burst length value of second memory element (DDR). Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.

Abstract translation: 一种用于降低功耗同时提高便携式计算设备的存储器管理单元的效率的方法和系统包括确定存储器请求的数据是否存在于存储器管理单元外部的第一存储器元件内。 第一存储器元件可以包括高速缓存。 如果存储器请求的数据不存在于第一存储器元件内，则可以确定存储器请求的突发长度值的大小。 随后，可以使用与第二存储器元件（DDR）的突发长度值的大小对应的第二存储器元件（例如DDR（双数据速率）存储器）进行页表移动。 每个存储器请求可以包括描述符。 描述符可以具有保留字段区域，其包括预取提示，其指示第二存储器元素中的下一个描述符是否有效。

公开(公告)号：US10121001B1

公开(公告)日：2018-11-06

申请号：US15629516

申请日：2017-06-21

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Satyaki Mukherjee

IPC: G06F7/04 ,  G06F21/55 ,  G06F9/455 ,  G06F9/48

Abstract: Systems for a method for monolithic workload scheduling in a portable computing device (“PCD”) having a hypervisor are disclosed. An exemplary method comprises instantiating a primary virtual machine at a first exception level, wherein the primary virtual machine comprises a monolithic scheduler configured to allocate workloads within and between one or more guest virtual machines in response to one or more interrupts, instantiating a secure virtual machine at the first exception level and instantiating one or more guest virtual machines at the first exception level as well. When an interrupt is received at a hypervisor associated with a second exception level, the interrupt is forwarded to the monolithic scheduler along with hardware usage state data and guest virtual machine usage state data. The monolithic scheduler may, in turn, generate one or more context switches which may comprise at least one intra-VM context switch and at least one inter-VM context switch.

公开(公告)号：US20200285584A1

公开(公告)日：2020-09-10

申请号：US16292178

申请日：2019-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： Raghavendra Srinivas ,  Kaustav Roychowdhury ,  Siddesh Halavarthi Math Revana ,  Srivatsa Vaddagiri ,  Satyaki Mukherjee

IPC: G06F12/0891 ,  G06F12/0837 ,  G06F12/0842 ,  G06F12/0897

Abstract: Aborting a cache memory flush may include initiating a flush operation in which a plurality of cache lines are flushed from a cache memory associated with a processor core that is entering a power collapse mode. Assertion of a wake-up signal associated with the processor core entering the power collapse mode may be detected. The wake-up signal may occur before completion of the flush operation. The flush operation may cease or abort in response to detecting the wake-up signal.

公开(公告)号：US20170031838A1

公开(公告)日：2017-02-02

申请号：US14811296

申请日：2015-07-28

Applicant: QUALCOMM Incorporated

Inventor： Satyaki Mukherjee ,  Subodh Singh ,  Ajaykumar Shankargouda Patil ,  Thomas Zeng ,  Azzedine Touzni

IPC: G06F12/14 ,  G06F9/455

CPC classification number: G06F12/1441 ,  G06F9/45558 ,  G06F12/1009 ,  G06F21/53 ,  G06F21/85 ,  G06F2009/45587 ,  G06F2212/1016 ,  G06F2212/1052 ,  G06F2212/657

Abstract: Disclosed is a method for protecting virtual machine data at a peripheral subsystem connected to at least one processor configured to host a plurality of virtual machines. In the method, context information, including a virtual machine identifier (VMID), is received. The VMID is unique to one of the plurality of virtual machines. A storage bank of a plurality of storage banks is selected based on the VMID included in the received context information. Each storage bank of the plurality of storage banks uses a same bus address range. A data bus is connected to the selected storage bank.

Abstract translation: 公开了一种用于在与被配置为托管多个虚拟机的至少一个处理器连接的外围子系统上保护虚拟机数据的方法。 在该方法中，接收包括虚拟机标识符（VMID）的上下文信息。 VMID对于多个虚拟机之一是唯一的。 基于接收到的上下文信息中包含的VMID来选择多个存储体的存储体。 多个存储组的每个存储体使用相同的总线地址范围。 数据总线连接到选定的存储库。

公开(公告)号：US20150286269A1

公开(公告)日：2015-10-08

申请号：US14243706

申请日：2014-04-02

Applicant: QUALCOMM INCORPORATED

Inventor： Sreekumar Padmanabhan ,  Satyaki Mukherjee

IPC: G06F1/32 ,  G06F12/10 ,  G06F12/12

CPC classification number: G06F1/3275 ,  G06F12/0862 ,  G06F12/1027 ,  G06F12/123 ,  G06F2212/654 ,  Y02D10/14

Abstract: A method and system for reducing power consumption while improving efficiency of a memory management unit of a portable computing device are described. The method and system include determining if data of a memory request exists within a first memory element external to the memory management unit. The first memory element may include a cache. If the data of the memory request does not exist within the first memory element, then a magnitude of a burst length value of the memory request may be determined. Subsequently, a page table walk may be conducted with a second memory element, such as DDR memory, that corresponds with the magnitude of the burst length value of the memory request. Each memory request may include a descriptor. The descriptor may have a reserved field region that includes a pre-fetch hint which indicates whether next descriptors in the second memory element are valid or not.

Abstract translation: 描述了一种用于在提高便携式计算设备的存储器管理单元的效率的同时降低功耗的方法和系统。 所述方法和系统包括确定存储器请求的数据是否存在于存储器管理单元外部的第一存储器元件内。 第一存储器元件可以包括高速缓存。 如果存储器请求的数据不存在于第一存储器元件内，则可以确定存储器请求的突发长度值的大小。 随后，可以利用对应于存储器请求的突发长度值的大小的第二存储器元件（例如DDR存储器）来进行页表移动。 每个存储器请求可以包括描述符。 描述符可以具有保留字段区域，其包括预取提示，其指示第二存储器元素中的下一个描述符是否有效。

公开(公告)号：US10769073B2

公开(公告)日：2020-09-08

申请号：US15939031

申请日：2018-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： Kunal Desai ,  Satyaki Mukherjee ,  Siddharth Kamdar ,  Abhinav Mittal ,  Vinayak Shrivastava

IPC: G06F12/10 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.