公开(公告)号：US20160344374A1

公开(公告)日：2016-11-24

申请号：US14720634

申请日：2015-05-22

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Steven James DILLEN ,  Animesh DATTA ,  Zhengyu DUAN ,  Satyanarayana SAHU ,  Praveen NARENDRANATH

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/012 ,  H03K3/037 ,  H03K5/131

Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

Abstract translation: 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在延迟模块输出端提供功能上的I1IA，其中I1是I的函数，IA是IN0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，IN0是第一个 净输入。

公开(公告)号：US20160365856A1

公开(公告)日：2016-12-15

申请号：US14736213

申请日：2015-06-10

Applicant: QUALCOMM Incorporated

Inventor： Qi YE ,  Zhengyu DUAN ,  Steven James DILLEN ,  Animesh DATTA

IPC: H03K19/00 ,  H03K3/3562

CPC classification number: H03K19/0013 ,  G01R31/318541 ,  G06F1/04 ,  H03K3/037 ,  H03K3/35625

Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

Abstract translation: MOS器件包括配置有一个锁存器反馈F并被配置为接收锁存器输入I和锁存时钟C的第一锁存器。第一锁存器被配置为输出Q，其中输出Q是CF，IF和IC的函数 并且锁存反馈F是输出Q的函数。第一锁存器可以包括串联堆叠的第一组晶体管，其中第一组晶体管包括至少五个晶体管。 MOS器件还可以包括耦合到第一锁存器的第二锁存器。 第二锁存器可以被配置为扫描模式下的锁存器和功能模式中的脉冲锁存器。 第一锁存器可以作为主锁存器操作，并且第二锁存器可以在扫描模式期间作为从锁存器操作。

公开(公告)号：US20160211846A1

公开(公告)日：2016-07-21

申请号：US14598182

申请日：2015-01-15

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Steven James DILLEN ,  Animesh DATTA

IPC: H03K19/00 ,  H03K17/687

CPC classification number: H03K19/0016 ,  H03K17/6872

Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Abstract translation: CGC包括使能模块和锁存模块。 启用模块具有使能模块输入和使能模块输出。 锁存模块具有锁存模块输入和锁存模块输出。 锁存模块输入包括用于接收时钟的锁存模块时钟输入和用于接收使能模块输出的锁存模块使能输入。 锁存模块使能输入耦合到使能模块输出。 锁存模块被配置为通过基于使能模块输入的锁存模块输出来启用和禁用时钟。 锁存模块包括作为锁存模块输出的内部使能节点。 锁存模块被配置为使内部使能节点根据使能模块输出和ĒC的功能从低电平转换到高电平，其中E是内部使能节点，C是时钟。