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公开(公告)号：US12056804B2
公开(公告)日：2024-08-06
申请号：US18317825
申请日：2023-05-15
Applicant: QUALCOMM Incorporated
Inventor： Thomas Edwin Frisinger , Richard Hammerstone , Andrew Evan Gruber , Gang Zhong , Yun Du , Jonnala Gadda Nagendra Kumar
CPC classification number: G06T15/005 , G06F9/30101 , G06F9/30123 , G06T1/20 , G06T1/60 , G06T15/80
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
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公开(公告)号：US11373267B2
公开(公告)日：2022-06-28
申请号：US16673564
申请日：2019-11-04
Applicant: QUALCOMM Incorporated
Inventor： Tao Wang , Shambhoo Khandelwal , Andrew Evan Gruber , Shangmei Yu , Jing Gao , Junmei Shao , Thomas Edwin Frisinger , Rick Hammerstone
Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
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公开(公告)号：US10157443B1
公开(公告)日：2018-12-18
申请号：US15662933
申请日：2017-07-28
Applicant: QUALCOMM Incorporated
Abstract: The techniques of this disclosure include deferred batching of incremental constant loads. Graphics APIs include the ability to use lightweight constants for use by shaders. A buffer is allocated by a graphics processing unit (GPU) driver that contains a snapshot of the current lightweight constants. This may provide a complete set of state to serve as a starting point. From then on updates to the lightweight constants may be appended to this buffer in an incremental fashion by inserting the update and increasing the size of the buffer by a command processor on a graphics processing unit (GPU). The incremental nature of the updates may be captured, but removes the need for issuing them on every draw call and instead the incremental updates may be batch processed when a live draw call is encountered.
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公开(公告)号：US08931108B2
公开(公告)日：2015-01-06
申请号：US13769687
申请日：2013-02-18
Applicant: QUALCOMM Incorporated
Inventor： Colin Christopher Sharp , Sudeep Ravi Kottilingal , Thomas Edwin Frisinger , Andrew E. Gruber
CPC classification number: G06F21/53 , G06F21/10 , G06F21/50 , G06F21/74 , G06F2221/0746
Abstract: A graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.
Abstract translation: 图形处理单元（GPU）被配置为根据不安全模式和安全模式之一访问第一存储器单元。 GPU可以包括存储器访问控制器，其被配置为当GPU处于不安全模式时允许GPU仅从第一存储器单元的不安全部分读取数据，并且被配置为允许GPU将数据仅写入到 当GPU处于安全模式时的第一个存储单元。
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公开(公告)号：US20140237609A1
公开(公告)日：2014-08-21
申请号：US13769687
申请日：2013-02-18
Applicant: QUALCOMM INCORPORATED
Inventor： Colin Christopher Sharp , Sudeep Ravi Kottilingal , Thomas Edwin Frisinger , Andrew E. Gruber
IPC: G06F12/14
CPC classification number: G06F21/53 , G06F21/10 , G06F21/50 , G06F21/74 , G06F2221/0746
Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU comprises a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.
Abstract translation: 本公开提出了用于图形处理的技术。 在一个示例中，图形处理单元（GPU）被配置为根据不安全模式和安全模式之一访问第一存储器单元。 GPU包括存储器访问控制器，其被配置为当GPU处于不安全模式时允许GPU仅从第一存储器单元的不安全部分读取数据，并且被配置为允许GPU仅将数据写入到安全部分 当GPU处于安全模式时的第一个存储单元。
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Patent Agency Ranking
公开(公告)号：US12002142B2
公开(公告)日：2024-06-04
申请号：US17373718
申请日：2021-07-12
Applicant: QUALCOMM Incorporated
Inventor： Tushar Garg , Thomas Edwin Frisinger , Nigel Poole , Vishwanath Shashikant Nikam , Vijay Kumar Donthireddy
CPC classification number: G06T15/005 , G06F11/3485 , G06T1/20
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.
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公开(公告)号：US11321804B1
公开(公告)日：2022-05-03
申请号：US17071888
申请日：2020-10-15
Applicant: QUALCOMM Incorporated
Inventor： Thomas Edwin Frisinger , Richard Hammerstone , Jonnala Gadda Nagendra Kumar , Avinash Seetharamaiah , Shangmei Yu , Srihari Babu Alla
Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.
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公开(公告)号：US09489313B2
公开(公告)日：2016-11-08
申请号：US14035643
申请日：2013-09-24
Applicant: QUALCOMM Incorporated
Inventor： David A. Gotwalt , Thomas Edwin Frisinger , Andrew Evan Gruber , Eric Demers , Colin Christopher Sharp
CPC classification number: G06F12/1009 , G06F12/08 , G06F2212/302 , G06T1/60
Abstract: The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.
Abstract translation: 本公开提供了处理非居民页面的系统和方法，其可以包括尝试访问非驻留页面，非居民页面的地址指向包含默认值的存储器页面，确定非居民页面 页面不应基于指示特定非驻留页面不应生成页面错误的指示符，返回指示，读取的存储器未翻译并在非驻留页面的访问时返回默认值 是一个读取，非驻留页面不应该导致页面错误。 当非驻留页面的访问是写入而非驻留页面不应导致页面错误时，另一个示例可能会中断写入。
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公开(公告)号：US12056790B2
公开(公告)日：2024-08-06
申请号：US17758219
申请日：2020-01-31
Applicant: QUALCOMM Incorporated
Inventor： Yun Du , Andrew Evan Gruber , Chun Yu , Chihong Zhang , Thomas Edwin Frisinger , Richard Hammerstone , Zilin Ying , Heng Qi , Quanquan Xu , Sheng Gu
IPC: G06T1/60
CPC classification number: G06T1/60
Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.
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公开(公告)号：US20220122214A1
公开(公告)日：2022-04-21
申请号：US17071888
申请日：2020-10-15
Applicant: QUALCOMM Incorporated
Inventor： Thomas Edwin Frisinger , Richard Hammerstone , Jonnala Gadda Nagendra Kumar , Avinash Seetharamaiah , Shangmei Yu , Srihari Babu Alla
Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.
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