公开(公告)号：US20170085475A1

公开(公告)日：2017-03-23

申请号：US15080429

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Vijay Bantval ,  Jun Ho Bahn

IPC: H04L12/741 ,  H04L12/413 ,  H04L1/00 ,  H04L12/46 ,  H04L12/733

CPC classification number: H04L45/74 ,  H04L1/0018 ,  H04L12/4135 ,  H04L12/42 ,  H04L12/4637 ,  H04L45/22 ,  H04L45/306 ,  H04L49/102 ,  H04L49/109

Abstract: Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.

公开(公告)号：US10061581B2

公开(公告)日：2018-08-28

申请号：US14170193

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Jun Ho Bahn ,  Vijay Bantval

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3875

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

公开(公告)号：US09189438B2

公开(公告)日：2015-11-17

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。

公开(公告)号：US20150220339A1

公开(公告)日：2015-08-06

申请号：US14170193

申请日：2014-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan ,  Jun Ho Bahn ,  Vijay Bantval

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3875

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

Abstract translation: 这里描述了用于在加载/存储操作期间对数据向量执行动态格式转换的系统和方法。 在一个实施例中，一种用于将数据向量从存储器加载到向量单元中的方法包括从存储器读取多个样本，其中多个样本被打包在存储器中。 该方法还包括拆包样本以获得多个未打包的样本，并行地对未打包的样本执行格式转换，以及将格式转换的样本的至少一部分发送到向量单元。

公开(公告)号：US20140281112A1

公开(公告)日：2014-09-18

申请号：US13799286

申请日：2013-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： Hari Rao ,  Venugopal Boynapalli ,  Kevin Robert Bowles ,  Vijay Bantval

IPC: G06F13/40

CPC classification number: G06F13/40 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various aspects of dynamic power reduction in a bus communication architecture are described herein as embodied in an XBAR architecture that provides flexible gating of multiple paths and repeater circuitry to allow any of a number of selected clients to communicate with any of the other interconnected clients while reducing dynamic power consumption by disabling unused repeater circuitry in the bus communication architecture.

Abstract translation: 总线通信架构中的动态功率降低的各个方面在本文中被描述为体现在XBAR架构中，其提供多路径和中继器电路的灵活门控，以允许多个所选择的客户端中的任何一个与任何其他互连的客户端通信，同时减少 通过禁用总线通信架构中的未使用的中继器电路来实现动态功耗。