公开(公告)号：US09385778B2

公开(公告)日：2016-07-05

申请号：US14170274

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Gayatri Singaravelu

IPC: H04B1/00 ,  H04B1/7115 ,  H04B1/7083 ,  H04B1/7117 ,  H04B1/707 ,  H04B1/708

CPC classification number: H04B1/7115 ,  H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7117

Abstract: Systems and methods for despreading a received signal are described herein. In one embodiment, a vector processor comprises a plurality of code generators, wherein each code generator is configured to generate a different code corresponding to a different code hypothesis. The vector processor also comprises a plurality of despread blocks coupled to a common input for receiving samples of a signal, wherein each despread block is configured to despread at least a portion of the samples with a different one of the codes to generate respective despreaded samples and to accumulate the respective despreaded samples over a length of the code.

Abstract translation: 在此描述用于解扩接收信号的系统和方法。 在一个实施例中，向量处理器包括多个代码生成器，其中每个代码生成器被配置为生成对应于不同代码假设的不同代码。 矢量处理器还包括耦合到公共输入的多个解扩展块，用于接收信号的采样，其中每个去扩展块被配置为用不同的一个代码对至少一部分样本进行解扩，以产生相应的解扩样本， 以在代码的长度上累积各个解扩的样本。

公开(公告)号：US09276778B2

公开(公告)日：2016-03-01

申请号：US14170234

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Steve Hengchen Hsu ,  Gayatri Singaravelu

IPC: H04L25/02 ,  H04B1/7117 ,  G06F9/30 ,  H04B1/7115

CPC classification number: H04L25/0212 ,  G06F9/30 ,  G06F9/30036 ,  H04B1/7115 ,  H04B1/7117 ,  H04L25/0204 ,  H04L25/0224

Abstract: Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Abstract translation: 这里描述了用于在矢量处理器上执行耙指操作的系统和方法。 在一个实施例中，一种用于耙指处理的方法包括将来自寄存器的样本加载到执行单元中，对执行单元中的样本执行耙指操作，以及将来自耙指操作的结果写入寄存器。 执行耙指操作包括执行有限脉冲响应（FIR）滤波操作，并且执行解扩操作，其中来自FIR滤波器操作的滤波后的采样被输入到解扩操作而不经过寄存器。

公开(公告)号：US20150143086A1

公开(公告)日：2015-05-21

申请号：US14082088

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan

IPC: G06F9/30

CPC classification number: G06F9/30181 ,  G06F7/76 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8076

Abstract: Vector processing engines (VPEs) employing format conversion circuitry in data flow paths between vector data memory and execution units to provide in-flight format-converting of input vector data to execution units for vector processing operations are disclosed. Related vector processor systems and methods are also disclosed. Format conversion circuitry is provided in data flow paths between vector data memory and execution units in the VPE. The format conversion circuitry is configured to convert input vector data sample sets fetched from vector data memory in-flight while the input vector data sample sets are being provided over the data flow paths to the execution units to be processed. In this manner, format conversion of the input vector data sample sets does not require pre-processing, storage, and re-fetching from vector data memory, thereby reducing power consumption and not limiting efficiency of the data flow paths by format conversion pre-processing delays.

Abstract translation: 公开了在向量数据存储器和执行单元之间的数据流路径中采用格式转换电路的矢量处理引擎（VPE），以向输入矢量数据提供转换为执行单元的向量处理操作。 还公开了相关矢量处理器系统和方法。 在VPE中的矢量数据存储器和执行单元之间的数据流路径中提供格式转换电路。 格式转换电路被配置为将输入矢量数据样本集合在数据流路径上提供给要处理的执行单元的同时，将从输入向量数据存储器中取出的输入向量数据样本集合进行转换。 以这种方式，输入向量数据样本集的格式转换不需要从向量数据存储器进行预处理，存储和重新获取，从而通过格式转换预处理来降低功耗并且不限制数据流路径的效率 延误

公开(公告)号：US10159053B2

公开(公告)日：2018-12-18

申请号：US15251581

申请日：2016-08-30

Applicant: QUALCOMM Incorporated

Inventor： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

IPC: H04W56/00 ,  H04L7/02 ,  H04W52/02 ,  G06F13/42

Abstract: Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

公开(公告)号：US09979432B2

公开(公告)日：2018-05-22

申请号：US15420520

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Scott Cheng ,  Pascal Philippe ,  Graig Zethner ,  Vaidyanathan Seetharaman ,  Kanwal Preet S. Banga ,  Srinivas Badam

IPC: H04B1/38 ,  H04B1/40 ,  H04L29/08

CPC classification number: H04B1/40 ,  H04B17/318 ,  H04L69/323 ,  H04L69/324

Abstract: A serial transceiver that includes programmable distributed data processing is provided. The serial transceiver can include an ingress channel that receives serial ingress data and an egress channel that transmits serial egress data. The serial transceiver can also include first and second layers that are one and another of a transport layer, a link layer, or a physical layer (PHY). The first and second layers can include elements that process the ingress data and the egress data. The serial transceiver can also include a programmable controller, a first interconnect that connects the programmable controller to the first layer, and a second interconnect that connects the programmable controller to the second layer. The programmable controller can send first data via the first interconnect to the first layer, and the first data can be processed by one of the first layer elements.

公开(公告)号：US20170085475A1

公开(公告)日：2017-03-23

申请号：US15080429

申请日：2016-03-24

Applicant: QUALCOMM Incorporated

Inventor： Scott Wang-Yip Cheng ,  Raheel Khan ,  Vijay Bantval ,  Jun Ho Bahn

IPC: H04L12/741 ,  H04L12/413 ,  H04L1/00 ,  H04L12/46 ,  H04L12/733

CPC classification number: H04L45/74 ,  H04L1/0018 ,  H04L12/4135 ,  H04L12/42 ,  H04L12/4637 ,  H04L45/22 ,  H04L45/306 ,  H04L49/102 ,  H04L49/109

Abstract: Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.

公开(公告)号：US09418041B2

公开(公告)日：2016-08-16

申请号：US14157441

申请日：2014-01-16

Applicant: QUALCOMM Incorporated

Inventor： Samuel Sangmin Rhee ,  Hung-Chih Lai ,  Dong Wook Seo ,  Raheel Khan

IPC: G06F9/00 ,  G06F15/78 ,  G06F9/30 ,  G06F17/14 ,  G06F9/38

CPC classification number: G06F15/78 ,  G06F9/30036 ,  G06F9/3885 ,  G06F17/14

Abstract: Systems and method for reading data samples in reverse group order are described herein according to various embodiments of the present disclosure. In one embodiment, a method for reading data samples in a memory is provided, wherein the data samples correspond to an operand of a vector operation, the data samples are grouped into a plurality of different groups, and the different groups are spaced apart by a plurality of addresses in the memory. The method comprises reading the groups of data samples in reverse group order, and, for each group, reading the data samples in the group in forward order.

Abstract translation: 根据本公开的各种实施例在此描述用于以反向组顺序读取数据样本的系统和方法。 在一个实施例中，提供了一种用于在存储器中读取数据样本的方法，其中数据样本对应于向量操作的操作数，数据样本被分组成多个不同的组，并且不同的组被间隔开 存储器中的多个地址。 该方法包括以反向组顺序读取数据样本组，并且对于每个组，以正向顺序读取组中的数据样本。

公开(公告)号：US20150222453A1

公开(公告)日：2015-08-06

申请号：US14170234

申请日：2014-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Raheel Khan ,  Steve Hengchen Hsu ,  Gayatri Singaravelu

IPC: H04L25/02 ,  H04B1/7117

CPC classification number: H04L25/0212 ,  G06F9/30 ,  G06F9/30036 ,  H04B1/7115 ,  H04B1/7117 ,  H04L25/0204 ,  H04L25/0224

Abstract: Systems and methods for performing a rake-finger operation on a vector processor are described herein. In one embodiment, a method for rake-finger processing comprises loading samples from a register into an execution unit, performing a rake-finger operation on the samples in the execution unit, and writing results from the rake-finger operation to the register. Performing the rake-finger operation comprises performing a finite impulse response (FIR) filter operation, and performing a despread operation, wherein filtered samples from the FIR filter operation are input to the despread operation without going through the register.

Abstract translation: 这里描述了用于在矢量处理器上执行耙指操作的系统和方法。 在一个实施例中，一种用于耙指处理的方法包括将来自寄存器的样本加载到执行单元中，对执行单元中的样本执行耙指操作，以及将来自耙指操作的结果写入寄存器。 执行耙指操作包括执行有限脉冲响应（FIR）滤波操作，并且执行解扩操作，其中来自FIR滤波器操作的滤波后的采样被输入到解扩操作而不经过寄存器。

公开(公告)号：US20150143079A1

公开(公告)日：2015-05-21

申请号：US14082079

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Fahad Ali Mujahid ,  Afshin Shiravi

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing a tapped-delay line(s) for providing precision correlation/covariance vector processing operations with reduced sample re-fetching and/or power consumption are disclosed. The VPEs disclosed herein are configured to provide correlation/covariance vector processing operations, such as code division multiple access (CDMA) correlation/covariance vector processing operations as a non-limiting example. A tapped-delay line(s) is included in the data flow paths between memory and execution units in the VPE. The tapped-delay line (s) is configured to receive and provide an input vector data sample set to execution units for performing correlation/covariance vector processing operations. The tapped-delay line(s) is also configured to shift the input vector data sample set for each filter delay tap and provide the shifted input vector data sample set to the execution units, so the shifted input vector data sample set need not be re-fetched from the vector data file during the filter vector processing operations.

Abstract translation: 公开了采用采用延迟线的矢量处理引擎（VPE），用于提供精确的相关/协方差向量处理操作，具有减少的样本重新获取和/或功耗。 这里公开的VPE被配置为提供诸如码分多址（CDMA）相关/协方差矢量处理操作之类的相关/协方差向量处理操作作为非限制性示例。 在VPE中的存储器和执行单元之间的数据流路径中包含一个抽头延迟线。 抽头延迟线被配置为接收并提供设置为执行相关/协方差向量处理操作的执行单元的输入向量数据样本。 抽头延迟线还被配置为移位每个滤波器延迟抽头的输入矢量数据采样集，并将移位的输入矢量数据采样集提供给执行单元，因此移位的输入矢量数据采样集不需要重新 在过滤器矢量处理操作期间从矢量数据文件中提取。

公开(公告)号：US20150143077A1

公开(公告)日：2015-05-21

申请号：US14082073

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3887 ,  G06F9/3897 ,  G06F15/8053

Abstract: Vector processing engines (VPEs) employing merging circuitry in data flow paths between execution units and vector data memory to provide in-flight merging of output vector data stored to vector data memory are disclosed. Related vector processing instructions, systems, and methods are also disclosed. Merging circuitry is provided in data flow paths between execution units and vector data memory in the VPE. The merging circuitry is configured to merge an output vector data sample set from execution units as a result of performing vector processing operations in-flight while the output vector data sample set is being provided over the output data flow paths from the execution units to the vector data memory to be stored. The merged output vector data sample set is stored in a merged form in the vector data memory without requiring additional post-processing steps, which may delay subsequent vector processing operations to be performed in execution units.

Abstract translation: 公开了在执行单元和向量数据存储器之间的数据流路径中采用合并电路的向量处理引擎（VPE），以提供存储到向量数据存储器中的输出矢量数据的飞行中合并。 还公开了相关向量处理指令，系统和方法。 在VPE中的执行单元和向量数据存储器之间的数据流路径中提供合并电路。 合并电路被配置为作为执行向量处理操作的结果，从执行单元合并输出向量数据样本集合，同时输出向量数据样本集被提供在从执行单元到向量的输出数据流路径上 要存储的数据存储器。 合并的输出向量数据样本集以合并形式存储在向量数据存储器中，而不需要额外的后处理步骤，这可能会延迟在执行单元中执行的后续向量处理操作。