公开(公告)号：US11437379B2

公开(公告)日：2022-09-06

申请号：US17025211

申请日：2020-09-18

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Deepak Sharma ,  Bharani Chava ,  Hyeokjin Lim ,  Peijie Feng ,  Seung Hyuk Kang ,  Jonghae Kim ,  Periannan Chidambaram ,  Kern Rim ,  Giridhar Nallapati ,  Venugopal Boynapalli ,  Foua Vang

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/095 ,  H01L23/528 ,  H01L29/78 ,  H03K19/0185

Abstract: Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

公开(公告)号：US11361817B2

公开(公告)日：2022-06-14

申请号：US17002082

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Changho Jung ,  Sung Son ,  Jason Cheng ,  Yandong Gao ,  Chulmin Jung ,  Venugopal Boynapalli

IPC: G11C16/04 ,  G11C11/4096 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4094

Abstract: A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

公开(公告)号：US10600866B2

公开(公告)日：2020-03-24

申请号：US15886611

申请日：2018-02-01

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L23/535 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

公开(公告)号：US09071239B2

公开(公告)日：2015-06-30

申请号：US13799686

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Sei Seung Yoon ,  Esin Terzioglu ,  Hari Ananthanarayanan ,  Venugopal Boynapalli

IPC: H03K17/00 ,  G11C7/10 ,  G11C7/02

CPC classification number: H03K17/002 ,  G11C7/02 ,  G11C7/10 ,  G11C7/1006

Abstract: A semiconductor apparatus is provided herein for reducing power when transmitting data between a first device and a second device in the semiconductor apparatus. Additional circuitry is added to the semiconductor apparatus to create a communication system that decreases a number of state changes for each signal line of a data bus between the first device and the second device for all communications. The additional circuitry includes a decoder coupled to receive and convert a value from the first device for transmission over the data bus to an encoder that provides a recovered (i.e., re-encoded) version of the value to the second device. One or more multiplexers may also be included in the additional circuitry to support any number of devices.

Abstract translation: 本发明提供一种半导体装置，用于在半导体装置中的第一装置和第二装置之间传输数据时降低功率。 向半导体装置添加附加电路以创建通信系统，该通信系统减少用于所有通信的第一设备和第二设备之间的数据总线的每个信号线的状态变化的数量。 附加电路包括解码器，其耦合以接收和转换来自第一设备的值，用于通过数据总线传输到向第二设备提供值的恢复（即重新编码）版本的编码器。 一个或多个多路复用器也可以包括在附加电路中以支持任何数量的设备。

公开(公告)号：US10784345B2

公开(公告)日：2020-09-22

申请号：US16781856

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

公开(公告)号：US20190088591A1

公开(公告)日：2019-03-21

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

公开(公告)号：US09806717B2

公开(公告)日：2017-10-31

申请号：US15289740

申请日：2016-10-10

Applicant: QUALCOMM Incorporated

Inventor： Kevin Robert Bowles ,  Jose Gabriel Corona ,  Venugopal Boynapalli

IPC: H03L5/00 ,  H03K19/0185 ,  H03K3/356 ,  H03K17/00

CPC classification number: H03K19/018528 ,  H03K3/35613 ,  H03K17/002 ,  H03K17/005 ,  H03K19/018507

Abstract: Systems and methods for level-shifting multiplexing are described herein. In one embodiment, a method for level-shifting multiplexing comprises selecting one of a plurality of inputs based on one or more select signals, and pulling down one of first and second nodes based on a logic state of the selected one of the plurality of inputs. The method also comprises pulling up the first node if the second node is pulled down, and pulling up the second node if the first node is pulled down.

公开(公告)号：US09755618B1

公开(公告)日：2017-09-05

申请号：US15061055

申请日：2016-03-04

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H03K3/12 ,  H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

公开(公告)号：US20150100842A1

公开(公告)日：2015-04-09

申请号：US14046084

申请日：2013-10-04

Applicant: QUALCOMM Incorporated

Inventor： Hari Rao ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli ,  Sagar Suresh Sabade ,  Bilal Zafar

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/3185 ,  G01R31/318516 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/022 ,  G11C29/12

Abstract: A reconfigurable instruction cell array (RICA) is provided that includes a plurality of master switch boxes that are configured to read and write from a plurality of buffers through a cross-bar switch. A master built-in-self-test (MBIST) engine is configured to drive a test word into the write path of at least one master switch box and to control the cross-bar switch so that the driven test word is broadcast to all the buffers for storage. The MBIST engine is also configured to retrieve the stored test words from the buffers through a read bus within the cross-bar switch.

Abstract translation: 提供了可重构指令单元阵列（RICA），其包括多个主开关盒，其被配置为通过交叉开关从多个缓冲器读取和写入。 主内置自检（MBIST）引擎被配置为将测试字驱动到至少一个主开关盒的写入路径中并且控制交叉开关，使得驱动的测试字广播到所有 用于存储的缓冲区 MBIST引擎还被配置为通过交叉开关中的读总线从缓冲器中检索存储的测试字。

公开(公告)号：US11710733B2

公开(公告)日：2023-07-25

申请号：US16808336

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin Lim ,  Bharani Chava ,  Foua Vang ,  Seung Hyuk Kang ,  Venugopal Boynapalli

IPC: H01L27/02 ,  H03K19/0185 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/528 ,  H03K19/018557

Abstract: A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mth track, where 2≤m m*P.