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    Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods
    1.
    发明授权
    Static random access memories (SRAM) with read-preferred cell structures, write drivers, related systems, and methods 有权
    具有读优选单元结构的静态随机存取存储器（SRAM），写入驱动器，相关系统和方法

    公开(公告)号：US09111635B2

    公开(公告)日：2015-08-18

    申请号：US13869110

    申请日：2013-04-24

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

    Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

    Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

    SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT
    3.
    发明申请
    SRAM READ PREFERRED BIT CELL WITH WRITE ASSIST CIRCUIT 有权
    SRAM读取具有写入辅助电路的优选位单元

    公开(公告)号：US20140036578A1

    公开(公告)日：2014-02-06

    申请号：US13741869

    申请日：2013-01-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

    Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

    DUAL WRITE WORDLINE MEMORY CELL
    5.
    发明申请
    DUAL WRITE WORDLINE MEMORY CELL 有权
    双写WORDLINE MEMORY CELL

    公开(公告)号：US20150380080A1

    公开(公告)日：2015-12-31

    申请号：US14320024

    申请日：2014-06-30

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

    IPC: G11C11/419 ,  G11C5/06

    CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

    Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

    Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。

    SRAM read preferred bit cell with write assist circuit
    6.
    发明授权
    SRAM read preferred bit cell with write assist circuit 有权
    SRAM通过写辅助电路读取优先位单元

    公开(公告)号：US09583178B2

    公开(公告)日：2017-02-28

    申请号：US13741869

    申请日：2013-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/412 ,  G11C11/419

    Abstract: Methods and apparatuses for static memory cells. A static memory cell may include a first pass gate transistor including a first back gate node and a second pass gate transistor including a second back gate node. The static memory cell may include a first pull down transistor including a third back gate node and a second pull down transistor including a fourth back gate node. The source node of the first pull down transistor, source node of the second pull down transistor, and first, second, third, and fourth back gate nodes are electrically coupled to each other to form a common node.

    Abstract translation: 静态存储单元的方法和装置。 静态存储单元可以包括第一栅极晶体管，其包括第一背栅极节点和包括第二后栅极节点的第二栅极晶体管。 静态存储单元可以包括包括第三后栅极节点的第一下拉晶体管和包括第四背栅极节点的第二下拉晶体管。 第一下拉晶体管的源节点，第二下拉晶体管的源节点以及第一，第二，第三和第四后门节点彼此电耦合以形成公共节点。

    Seven-transistor static random-access memory bitcell with reduced read disturbance
    7.
    发明授权
    Seven-transistor static random-access memory bitcell with reduced read disturbance 有权

    公开(公告)号：US10037795B2

    公开(公告)日：2018-07-31

    申请号：US14499149

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

    STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS
    8.
    发明申请
    STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS 有权
    静态随机存取存储器（SRAM），具有读取优先级的单元结构，写驱动程序，相关系统和方法

    公开(公告)号：US20140211546A1

    公开(公告)日：2014-07-31

    申请号：US13869110

    申请日：2013-04-24

    Applicant: Industry-Academic Cooperation Foundation, Yonsei University ,  QUALCOMM INCORPORATED

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Bin Yang ,  Zhongze Wang ,  Choh fei Yeap

    IPC: G11C11/412

    CPC classification number: G11C11/412 ,  G11C11/417 ,  G11C11/419 ,  H01L27/0207 ,  H01L27/1104 ,  Y10T29/41

    Abstract: Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.

    Abstract translation: 公开了具有读优选单元结构和写驱动器的静态随机存取存储器（SRAM）。 在一个实施例中，SRAM具有六个晶体管位单元。 读优选位单元通过提供两个反相器来实现，每个反相器具有上拉晶体管，下拉晶体管和通过栅极晶体管。 每个上拉晶体管与反馈回路相关联。 反馈环路改善了随机的静态噪声容限。 每个晶体管具有宽度和长度。 传输栅晶体管的长度增加。 下拉晶体管的宽度彼此相等，并且也等于通过栅极晶体管的宽度。 通过栅极和下拉晶体管的宽度也可以相对于现有设计而增加。 也可以使用写辅助电路来提高性能。

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