公开(公告)号：US20160164507A1

公开(公告)日：2016-06-09

申请号：US14640672

申请日：2015-03-06

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Bagher VAHID FAR ,  Alireza KHALILI ,  Yashar RAJAVI ,  Amirpouya KAVOUSIAN

IPC: H03K5/00 ,  H03K3/013 ,  H03K3/012 ,  H03L7/00 ,  H03K3/017

CPC classification number: H03K5/00006 ,  H03B19/10 ,  H03B19/14 ,  H03K5/1565

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。

公开(公告)号：US20160099729A1

公开(公告)日：2016-04-07

申请号：US14605734

申请日：2015-01-26

Applicant: QUALCOMM Incorporated

Inventor： Yashar RAJAVI ,  Alireza KHALILI ,  Amirpouya KAVOUSIAN ,  Mohammad Mahdi GHAHRAMANI ,  Mohammad Bagher VAHID FAR

IPC: H04B1/04 ,  H04B15/04 ,  H04L7/00

CPC classification number: H03K4/023 ,  H03B19/10 ,  H03F3/24 ,  H03K3/0315 ,  H04B2001/0408

Abstract: A method, an apparatus, and a computer program product are provided. The apparatus outputs a first sinusoidal signal and a second sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the first sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the second sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a control voltage for the first buffer and the second buffer based on the combined digital signal.

Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出第一正弦信号和第二正弦信号，产生基于第一正弦信号具有25％占空比的第一数字信号，产生基于25％占空比的第二数字信号 在第二正弦信号上，组合第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且将组合的第二时钟频率加倍 数字信号以产生具有第三时钟频率的输出信号，该第三时钟频率是第一时钟频率的四倍。 该装置还基于组合的数字信号产生用于第一缓冲器和第二缓冲器的控制电压。

公开(公告)号：US20170019066A1

公开(公告)日：2017-01-19

申请号：US14801535

申请日：2015-07-16

Applicant: QUALCOMM Incorporated

Inventor： Mohammad FARAZIAN ,  Amirpouya KAVOUSIAN ,  Alireza KHALILI

IPC: H03B5/12

CPC classification number: H03B5/1256 ,  H03B5/08 ,  H03B5/12 ,  H03B5/1206

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for generating multiple oscillating signals. One example circuit generally includes a first voltage-controlled oscillator (VCO) having a first inductor and a second VCO having a second inductor in parallel with a third inductor, wherein the second and third inductors are disposed inside a loop of the first inductor and may behave as a magnetic dipole. The loop of the first inductor may be symmetrical, and a combined geometry of loops of the second and third inductors may be symmetrical. The coupling coefficient (k) between the first inductor and a combination of the second and third inductors may be small (e.g., k

Abstract translation: 本公开的某些方面提供了用于产生多个振荡信号的技术和装置。 一个示例电路通常包括具有第一电感器的第一压控振荡器（VCO）和具有与第三电感器并联的第二电感器的第二VCO，其中第二和第三电感器设置在第一电感器的环路内，并且可以 表现为磁偶极子。 第一电感器的环路可以是对称的，并且第二和第三电感器的环路的组合几何形状可以是对称的。 由于电路布局的对称几何形状，第一电感器和第二和第三电感器的组合之间的耦合系数（k）可能很小（例如，k <0.01）。 利用较小的k，第一和第二VCO的电感器可以彼此更靠近地放置，从而减少两个VCO消耗的面积。

公开(公告)号：US20150365062A1

公开(公告)日：2015-12-17

申请号：US14307355

申请日：2014-06-17

Applicant: QUALCOMM Incorporated

Inventor： Amirpouya KAVOUSIAN ,  Alireza KHALILI ,  Mohammad Bagher VAHID FAR

IPC: H03H11/00

CPC classification number: H03H7/0153 ,  H01Q1/52 ,  H01Q7/00 ,  H03H1/0007 ,  H03H2001/0078 ,  H04B3/28 ,  H05K1/0228 ,  H05K1/165

Abstract: A method and an apparatus for canceling EM coupling are provided. The apparatus includes a ring structure at least partially surrounding an EM circuit. A negative transconductance circuit is coupled to ends of the ring structure. The negative transconductance circuit is configured to cancel an EM coupling to the EM circuit at a frequency. The method includes generating a plurality of settings for a negative transconductance circuit and tuning the negative transconductance circuit to one of the plurality of settings for the negative transconductance circuit to cancel an EM coupling to an EM circuit at a frequency.

Abstract translation: 提供了用于消除EM耦合的方法和装置。 该装置包括至少部分地围绕EM电路的环形结构。 负跨导电路耦合到环结构的端部。 负跨导电路被配置为以一个频率消除与EM电路的EM耦合。 该方法包括产生用于负跨导电路的多个设置，并将负跨导电路调谐到用于负跨导电路的多个设置中的一个设置以消除以一频率对EM电路的EM耦合。