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1.发明申请CURRENT-DRIVEN BASEBAND FILTER WITH REDUCED ADJACENT CHANNEL LEAKAGE RATIO (ACLR) 有权具有降低相邻通道泄漏比（ACLR）的电流驱动滤波滤波器公开(公告)号：US20160336910A1
公开(公告)日：2016-11-17
申请号：US14711194
申请日：2015-05-13
CPC分类号： H03F3/19 , H03F1/0205 , H03F3/45179 , H03F2200/294 , H03F2200/451 , H03F2203/45306 , H04B1/1036 , H04B2001/1045
摘要： Certain aspects of the present disclosure provide methods and apparatus for processing an input signal. One example apparatus is a circuit that generally includes an amplifier, comprising a first transistor and a second transistor connected in cascode with the first transistor; a buffer coupled to an output of the amplifier and configured to provide feedback to the amplifier; and a current source coupled to the second transistor and incorporated into a loop of the feedback to the amplifier.
摘要翻译： 本公开的某些方面提供了用于处理输入信号的方法和装置。 一个示例性装置是通常包括放大器的电路，包括与第一晶体管共栅共享的第一晶体管和第二晶体管; 耦合到所述放大器的输出并被配置为向所述放大器提供反馈的缓冲器; 以及电流源，耦合到第二晶体管并且并入到放大器的反馈回路中。
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2.发明申请APPARATUS AND METHOD FOR GENERATING QUADRUPLED REFERENCE CLOCK FROM SINGLE-ENDED CRYSTAL OSCILLATOR 有权用于从单端晶体振荡器产生四参考时钟的装置和方法公开(公告)号：US20160164507A1
公开(公告)日：2016-06-09
申请号：US14640672
申请日：2015-03-06
CPC分类号： H03K5/00006 , H03B19/10 , H03B19/14 , H03K5/1565
摘要： A method, an apparatus, and a computer program product are provided. The apparatus outputs a sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a first control voltage and a second control voltage for the first buffer and a third control voltage for the second buffer based on the output signal.
摘要翻译： 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出正弦信号，产生基于正弦信号的具有25％占空比的第一数字信号，产生基于正弦信号具有25％占空比的第二数字信号， 第一数字信号和第二数字信号，以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且使组合数字信号的第二时钟频率加倍，以产生具有 第三个时钟频率是第一个时钟频率的四倍。 该装置还基于输出信号产生用于第一缓冲器的第一控制电压和第二控制电压以及第二缓冲器的第三控制电压。
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公开(公告)号：US20160254817A1
公开(公告)日：2016-09-01
申请号：US14743360
申请日：2015-06-18
CPC分类号： H03L7/0802 , H02M3/07 , H03L7/0891 , H03L7/093
摘要： Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.
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公开(公告)号：US20150365062A1
公开(公告)日：2015-12-17
申请号：US14307355
申请日：2014-06-17
IPC分类号： H03H11/00
CPC分类号： H03H7/0153 , H01Q1/52 , H01Q7/00 , H03H1/0007 , H03H2001/0078 , H04B3/28 , H05K1/0228 , H05K1/165
摘要： A method and an apparatus for canceling EM coupling are provided. The apparatus includes a ring structure at least partially surrounding an EM circuit. A negative transconductance circuit is coupled to ends of the ring structure. The negative transconductance circuit is configured to cancel an EM coupling to the EM circuit at a frequency. The method includes generating a plurality of settings for a negative transconductance circuit and tuning the negative transconductance circuit to one of the plurality of settings for the negative transconductance circuit to cancel an EM coupling to an EM circuit at a frequency.
摘要翻译： 提供了用于消除EM耦合的方法和装置。 该装置包括至少部分地围绕EM电路的环形结构。 负跨导电路耦合到环结构的端部。 负跨导电路被配置为以一个频率消除与EM电路的EM耦合。 该方法包括产生用于负跨导电路的多个设置，并将负跨导电路调谐到用于负跨导电路的多个设置中的一个设置以消除以一频率对EM电路的EM耦合。
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5.发明申请METHODS AND APPARATUS FOR GENERATING TWO-TONE CALIBRATION SIGNALS FOR PERFORMING LINEARITY CALIBRATION 有权用于生成用于进行线性校准的两个校准信号的方法和装置公开(公告)号：US20150311989A1
公开(公告)日：2015-10-29
申请号：US14265078
申请日：2014-04-29
CPC分类号： H04B17/21 , H04L7/0331
摘要： Certain aspects of the present disclosure provide methods and apparatus for generating a two-tone signal for performing linearity calibration of a radio frequency (RF) circuit. One example apparatus generally includes a tone generating circuit configured to generate a first single-tone signal from a digital clock signal and a mixer connected with the tone generating circuit and configured to mix the first single-tone signal with a second single-tone signal to provide a two-tone signal having frequencies at a sum and a difference of frequencies of the first and second single-tone signals.
摘要翻译： 本公开的某些方面提供了用于生成用于执行射频（RF）电路的线性校准的双音信号的方法和装置。 一个示例性设备通常包括乐音发生电路，其被配置为从数字时钟信号产生第一单音信号，以及混音器，与音调发生电路相连，并配置为将第一单音信号与第二单音信号混合到 提供具有第一和第二单音信号的和频和频差的频率的双音信号。
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6.发明申请POWER-EFFICIENT, LOW-NOISE, AND PROCESS/VOLTAGE/TEMPERATURE (PVT)-INSENSITIVE REGULATOR FOR A VOLTAGE-CONTROLLED OSCILLATOR (VCO) 有权用于电压控制的振荡器（VCO）的功率有效，低噪声和工艺/电压/温度（PVT） - 感应稳压器公开(公告)号：US20150286235A1
公开(公告)日：2015-10-08
申请号：US14244321
申请日：2014-04-03
IPC分类号： G05F3/02
摘要： Certain aspects of the present disclosure provide voltage regulating circuits which are power efficient, low noise, and substantially insensitive to changes in process technology, power supply voltage, and temperature. Such circuits may be used to provide the regulated voltage for a voltage-controlled oscillator (VCO), for example, as found in a radio frequency front end (RFFE). One example voltage regulating circuit generally includes a current source configured to supply or sink a reference current and a current mirror having a bias branch and a main branch, wherein the bias branch is connected with the current source, wherein the main branch includes a source follower to provide the regulated voltage, and wherein the reference current is available at a node for the regulated voltage.
摘要翻译： 本公开的某些方面提供了功率有效，低噪声并且对工艺技术，电源电压和温度变化基本上不敏感的电压调节电路。 可以使用这样的电路来为例如在射频前端（RFFE）中找到的压控振荡器（VCO）提供调节电压。 一个示例性电压调节电路通常包括被配置为提供或吸收参考电流的电流源和具有偏压支路和主支路的电流镜，其中偏压支路与电流源连接，其中主支路包括源极跟随器 以提供调节电压，并且其中参考电流在用于调节电压的节点处可用。
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7.发明申请LEAKAGE COMPENSATION CIRCUIT FOR PHASE-LOCKED LOOP (PLL) LARGE THIN OXIDE CAPACITORS 审中-公开用于相位锁定环路（PLL）的大型氧化物电容器的泄漏补偿电路公开(公告)号：US20160373116A1
公开(公告)日：2016-12-22
申请号：US15257578
申请日：2016-09-06
CPC分类号： H03L7/0802 , H02M3/07 , H03L7/0891 , H03L7/093
摘要： Certain aspects of the present disclosure provide methods and apparatus for compensating, or at least adjusting, for capacitor leakage. One example method generally includes determining a leakage voltage corresponding to a leakage current of a capacitor in a filter for a phase-locked loop (PLL), wherein the determining comprises closing a set of switches for discontinuous sampling of the leakage voltage; based on the sampled leakage voltage, generating a sourced current approximately equal to the leakage current; and injecting the sourced current into the capacitor.
摘要翻译： 本公开的某些方面提供了用于补偿或至少调整电容器泄漏的方法和装置。 一个示例性方法通常包括确定对应于用于锁相环（PLL）的滤波器中的电容器的漏电流的泄漏电压，其中所述确定包括闭合一组开关以不连续地采样泄漏电压; 基于采样的泄漏电压，产生大致等于泄漏电流的源电流; 并将源电流注入电容器。
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8.发明申请FULLY I/Q BALANCED QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS 有权充分的I / Q平衡无线电频率混合器具有低噪声和低转换损耗公开(公告)号：US20160241192A1
公开(公告)日：2016-08-18
申请号：US14622591
申请日：2015-02-13
发明人： Cheng-Han WANG , Alberto CICALINI , Thinh Cat NGUYEN , Mohammad Bagher VAHID FAR , Jesse Aaron RICHMOND
CPC分类号： H03D7/145 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0027
摘要： A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.
摘要翻译： 提供了一种用于混合射频信号的方法，装置和系统产品。 一方面，该装置被配置为基于第一，第二，第三和第四相位半占空时钟信号来执行开关的切换。 该装置利用第一，第二，第三和第四相位半占空比时钟信号在差分输入端口上卷积差分输入信号，以同时产生差分同相输出信号和双差分上的差分正交相输出信号 输出端口 第一，第二，第三和第四相位半占空比时钟信号的频率相同，相位相差90度。
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公开(公告)号：US20160099729A1
公开(公告)日：2016-04-07
申请号：US14605734
申请日：2015-01-26
发明人： Yashar RAJAVI , Alireza KHALILI , Amirpouya KAVOUSIAN , Mohammad Mahdi GHAHRAMANI , Mohammad Bagher VAHID FAR
CPC分类号： H03K4/023 , H03B19/10 , H03F3/24 , H03K3/0315 , H04B2001/0408
摘要： A method, an apparatus, and a computer program product are provided. The apparatus outputs a first sinusoidal signal and a second sinusoidal signal according to a first clock frequency, generates, a first digital signal having a 25% duty cycle based on the first sinusoidal signal, generates a second digital signal having a 25% duty cycle based on the second sinusoidal signal, combines the first digital signal and the second digital signal to generate a combined digital signal having a 50% duty cycle and a second clock frequency that is double the first clock frequency, and doubles the second clock frequency of the combined digital signal to generate an output signal having a third clock frequency that is quadruple the first clock frequency. The apparatus further generates a control voltage for the first buffer and the second buffer based on the combined digital signal.
摘要翻译： 提供了一种方法，装置和计算机程序产品。 该装置根据第一时钟频率输出第一正弦信号和第二正弦信号，产生基于第一正弦信号具有25％占空比的第一数字信号，产生基于25％占空比的第二数字信号 在第二正弦信号上，组合第一数字信号和第二数字信号以产生具有50％占空比和第二时钟频率的组合数字信号，该第二时钟频率是第一时钟频率的两倍，并且将组合的第二时钟频率加倍 数字信号以产生具有第三时钟频率的输出信号，该第三时钟频率是第一时钟频率的四倍。 该装置还基于组合的数字信号产生用于第一缓冲器和第二缓冲器的控制电压。
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