公开(公告)号：US20190086946A1

公开(公告)日：2019-03-21

申请号：US16193410

申请日：2018-11-16

Applicant: QUALCOMM Incorporated

Inventor： Martin SAINT-LAURENT ,  Lam HO ,  Carlos Andres RODRIGUEZ ANCER ,  Bhavin SHAH

IPC: G06F1/03 ,  H03K5/131 ,  H03K3/012 ,  G06F1/08 ,  G06F1/10 ,  H03K21/40 ,  G06F1/32

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

公开(公告)号：US20210124387A1

公开(公告)日：2021-04-29

申请号：US17143124

申请日：2021-01-06

Applicant: QUALCOMM Incorporated

Inventor： Martin SAINT-LAURENT ,  Lam HO ,  Carlos Andres RODRIGUEZ ANCER ,  Bhavin SHAH

IPC: G06F1/03 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/10 ,  H03K21/40 ,  G06F1/08 ,  H03K19/00 ,  H03K3/012 ,  H03K5/131

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.