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公开(公告)号:US20210124387A1
公开(公告)日:2021-04-29
申请号:US17143124
申请日:2021-01-06
Applicant: QUALCOMM Incorporated
Inventor: Martin SAINT-LAURENT , Lam HO , Carlos Andres RODRIGUEZ ANCER , Bhavin SHAH
IPC: G06F1/03 , G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/10 , H03K21/40 , G06F1/08 , H03K19/00 , H03K3/012 , H03K5/131
Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.
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公开(公告)号:US20190086946A1
公开(公告)日:2019-03-21
申请号:US16193410
申请日:2018-11-16
Applicant: QUALCOMM Incorporated
Inventor: Martin SAINT-LAURENT , Lam HO , Carlos Andres RODRIGUEZ ANCER , Bhavin SHAH
Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.
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公开(公告)号:US20180066998A1
公开(公告)日:2018-03-08
申请号:US15260194
申请日:2016-09-08
Applicant: QUALCOMM Incorporated
Inventor: Ali Akbar MERRIKH , Martin SAINT-LAURENT , Mohammad GHASEMAZAR , Rajit CHANDRA , Mohamed ALLAM
CPC classification number: G01K1/20 , G01K1/14 , G01K7/01 , G01K7/427 , G01K15/005 , G06F1/206 , Y02D10/16
Abstract: A temperature sensor position offset error correction power implementation include monitors (e.g., digital power monitor/meter) to measure activity on a die, and uses the activity measurements to compute real-time temperature offsets by converting activity to power, which can be used in a simplified compact thermal model. A system on chip including the die receives a temperature measurement of a region of the system on chip from a sensor. Power consumed by the region is estimated based on the measured activity, and temperature measurement of the system on chip is adjusted based on the estimated power.
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