公开(公告)号：US20190252408A1

公开(公告)日：2019-08-15

申请号：US15895094

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Xiangdong CHEN ,  Renukprasad HIREMATH ,  Rui LI ,  Venugopal BOYNAPALLI

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11816 ,  H01L2027/11855 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.

公开(公告)号：US20210405973A1

公开(公告)日：2021-12-30

申请号：US16913631

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Rui LI ,  De LU ,  Venkat NARAYANAN ,  Srivatsan CHELLAPPA

IPC: G06F7/58

Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

公开(公告)号：US20180068714A1

公开(公告)日：2018-03-08

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin LIANG ,  Tony Chung Yiu KWOK ,  Rui LI ,  Sei Seung YOON

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：US20230007601A1

公开(公告)日：2023-01-05

申请号：US17779464

申请日：2020-12-11

Applicant: Qualcomm Incorporated

Inventor： Harish VENKATACHARI ,  Paolo MINERO ,  Rui LI ,  Qian MA ,  Antriksh PANY ,  Masoud AZMOODEH ,  Yu FU ,  Ashwin ALUR SREESHA ,  Rimal PATEL ,  Arpit CHITRANSH

IPC: H04W52/52 ,  H04B17/318 ,  H04W52/24

Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may operate in a dual-connectivity (DC) configuration, and may measure signals from more than one radio access technology (RAT). The UE may receive a first signal power for a first RAT and a second signal power for a second RAT. The UE may determine a common gain state for the first RAT and the second RAT based on the first signal power and the second signal power. The UE may then apply the common gain state to a first receiver chain within the UE for the first RAT and to a second receiver chain within the UE for the second RAT, where the first receiver chain and the second receiver chain share at least one shared low noise amplifier (LNA).

公开(公告)号：US20220270938A1

公开(公告)日：2022-08-25

申请号：US17180652

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Saravanan MARIMUTHU ,  De LU ,  Baldeo Sharan SHARMA ,  Peeyush Kumar PARKAR ,  Venkat NARAYANAN ,  Rui LI ,  Samy Shafik Tawfik ZAYNOUN ,  Min CHEN ,  David KIDD ,  Amit PATIL

IPC: H01L21/66 ,  G06F30/398

Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

公开(公告)号：US20220247391A1

公开(公告)日：2022-08-04

申请号：US17162647

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Rui LI ,  De LU ,  Venkat NARAYANAN

IPC: H03K3/037 ,  H03K19/20 ,  H04B1/40

Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

公开(公告)号：US20190028087A1

公开(公告)日：2019-01-24

申请号：US15867206

申请日：2018-01-10

Applicant: QUALCOMM Incorporated

Inventor： Wei ZHUO ,  Timothy Donald GATHMAN ,  Wenbang XU ,  Li-chung CHANG ,  Rui LI ,  Rahul KARMAKER

IPC: H03H11/02

Abstract: A filter circuit may include a first path having a first complex baseband filter. The circuit may further include a second path having a second complex baseband filter. The circuit may further include a combiner coupled to an output of the first complex baseband filter and an output of the second complex baseband filter.

公开(公告)号：US20230223054A1

公开(公告)日：2023-07-13

申请号：US17574431

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Rui LI ,  De LU ,  Venkat NARAYANAN

IPC: G11C7/10

CPC classification number: G11C7/1009 ,  G11C7/1087

Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.