公开(公告)号：US11533075B1

公开(公告)日：2022-12-20

申请号：US17478163

申请日：2021-09-17

Applicant: QUALCOMM Incorporated

Inventor： Xinmin Yu ,  Bon-Hyun Ku ,  Yunfei Feng ,  Chuan Wang

IPC: H04B1/40 ,  H03F3/24

Abstract: An apparatus includes a transformer including a first inductor, a second inductor, and a third inductor. The apparatus also includes a power amplifier having an output coupled to the first inductor, a low-noise amplifier having an input coupled to a first terminal of the third inductor, and a fourth inductor having a first terminal and a second terminal, wherein the second terminal of the fourth inductor is coupled to a second terminal of the third inductor. The apparatus also includes a switch coupled between the first terminal of the third inductor and the first terminal of the fourth inductor.

公开(公告)号：US20190172635A1

公开(公告)日：2019-06-06

申请号：US16210976

申请日：2018-12-05

Applicant: Qualcomm Incorporated

Inventor： Bon-Hyun Ku ,  Hyunchul Park

IPC: H01F27/38 ,  H01F30/12 ,  H01Q3/36

Abstract: Methods and apparatuses can implement a phase shifter including at least one phase shift unit. In an example aspect, the phase shift unit has an inductive-capacitive (LC) core that includes an inductor to provide an inductance and a transistor to provide a capacitance using a parasitic capacitance thereof. In some implementations, the LC core includes a first connector node, a second connector node, a transistor, a first inductor, and a second inductor. The transistor is coupled between the first and second connector nodes and is configured to provide a capacitance to the LC core. The first inductor is coupled to the first connector node and is configured to provide a first inductance. The second inductor is coupled to the second connector node and is configured to provide a second inductance. Using a pi-type circuit topology for the LC core can reduce an insertion loss of the phase shift unit.

公开(公告)号：US10965261B2

公开(公告)日：2021-03-30

申请号：US16208398

申请日：2018-12-03

Applicant: Qualcomm Incorporated

Inventor： Jeremy Dunworth ,  Hyunchul Park ,  Bon-Hyun Ku ,  Vladimir Aparin

IPC: H03F3/21 ,  H03F3/195 ,  H03F3/213 ,  H03F1/56 ,  H03F3/45 ,  H03F1/02 ,  H03F3/30 ,  H03F3/345 ,  H03F3/193 ,  H03F3/24

Abstract: The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.

公开(公告)号：US10910714B2

公开(公告)日：2021-02-02

申请号：US15940888

申请日：2018-03-29

Applicant: QUALCOMM Incorporated

Inventor： Bon-Hyun Ku ,  Jeremy Dunworth

IPC: H01Q5/335 ,  H01Q1/22 ,  H01Q21/30 ,  H04B1/00 ,  H03H7/48 ,  H01Q21/28 ,  H04B1/44 ,  H03F1/02 ,  H03F1/56 ,  H03F3/21 ,  H03F3/68 ,  H03G1/00 ,  H04B1/525 ,  H01Q21/06 ,  H01Q1/24

Abstract: A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.