Patent search ap:("QUALCOMM Incorporated") AND inv:"Deping Huang" Page 1

1.

发明授权
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation 有权

公开(公告)号：US10520901B2

公开(公告)日：2019-12-31

申请号：US15904124

申请日：2018-02-23

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng Wu , Deping Huang , Jeffrey Mark Hinrichs , Marzio Pedrali-Noy

IPC: G04F10/04 , G04F10/00

Abstract: A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

$Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops$

2.

发明授权
Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops 有权

公开(公告)号：US10484027B2

公开(公告)日：2019-11-19

申请号：US15419981

申请日：2017-01-30

Applicant: QUALCOMM Incorporated

Inventor： Debesh Bhatta , Deping Huang , Jeffrey Mark Hinrichs

IPC: H04B1/04 , H03L7/081 , H03L7/093

Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.

3.

发明申请
CLOCK SCREENING WITH PROGRAMMABLE COUNTER-BASED CLOCK INTERFACE AND TIME-TO-DIGITAL CONVERTER WITH HIGH RESOLUTION AND WIDE RANGE OPERATION 审中-公开

公开(公告)号：US20190268010A1

公开(公告)日：2019-08-29

申请号：US15904124

申请日：2018-02-23

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng Wu , Deping Huang , Jeffrey Mark Hinrichs , Marzio Pedrali-Noy

IPC: H03L7/187 , H03L7/099 , H03L7/191 , H03L7/14

Abstract: A subranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

4.

发明授权
Clock screening with programmable counter-based clock interface and time-to-digital converter with high resolution and wide range operation 有权

公开(公告)号：US10707854B2

公开(公告)日：2020-07-07

申请号：US16684421

申请日：2019-11-14

Applicant: QUALCOMM Incorporated

Inventor： Zhengzheng Wu , Deping Huang , Jeffrey Mark Hinrichs , Marzio Pedrali-Noy

IPC: G04F10/04 , H03K5/26 , H03L7/099 , H03L7/14 , H03L7/187 , H03L7/191 , G04F10/00

Abstract: A sub-ranging time-to-digital converter (TDC) is disclosed that includes two ring oscillators for determining a time difference between two clock edges.

5.

发明申请
GLITCH FREE PHASE SELECTION MULTIPLEXER ENABLING FRACTIONAL FEEDBACK RATIOS IN PHASE LOCKED LOOPS 审中-公开

公开(公告)号：US20180138934A1

公开(公告)日：2018-05-17

申请号：US15419981

申请日：2017-01-30

Applicant: QUALCOMM Incorporated

Inventor： Debesh Bhatta , Deping Huang , Jeffrey Mark Hinrichs

IPC: H04B1/04 , H03K3/037 , H03L7/081 , H03L7/093

CPC classification number: H04B1/0483 , H03K5/1252 , H03L7/081 , H03L7/18

Abstract: In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.

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