公开(公告)号：US20250028341A1

公开(公告)日：2025-01-23

申请号：US18498927

申请日：2023-10-31

Applicant: QUALCOMM Incorporated

Inventor： Bengt Stefan GUSTAVSSON ,  Louis Dominic OLIVEIRA ,  Tomer SARAF ,  Robert John LITTRELL ,  Ganesh KIRAN ,  William Wei-Ting KUO

IPC: G05F1/56 ,  G06F1/10 ,  H03K5/125 ,  H03K5/24

Abstract: Aspects relate to mechanisms for detecting a voltage level on a data communication interface between a slave device and a host device. Based on the detected voltage level, the slave device may respond to the host device on the data communication interface at the detected voltage level. In some examples, the slave device may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface.

公开(公告)号：US20230046277A1

公开(公告)日：2023-02-16

申请号：US17403683

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Aram AKHAVAN ,  Kentaro YAMAMOTO ,  Lei SUN ,  Ganesh KIRAN

IPC: H03M1/16 ,  H03F3/45 ,  H03M1/12

Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

公开(公告)号：US20170093420A1

公开(公告)日：2017-03-30

申请号：US15014865

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Omid RAJAEE ,  Liang DAI ,  Ganesh KIRAN

IPC: H03M1/38 ,  H03M1/10

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.