公开(公告)号：US20160147247A1

公开(公告)日：2016-05-26

申请号：US14755435

申请日：2015-06-30

Applicant: QUALCOMM Incorporated

Inventor： Masoud ROHAM ,  Liang DAI

IPC: G05F3/26

CPC classification number: G05F3/262 ,  G01R19/0092 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2200/474 ,  H03F2200/91

Abstract: Certain aspects of the present disclosure generally relate to a low voltage, accurate current mirror, which may be used for distributed sensing of a remote current in an integrated circuit (IC). One example current mirror typically includes a first pair of transistors, a second pair of transistors in cascode with the first pair of transistors, a switching network coupled to the second pair of transistors, and a third pair of transistors coupled to the switching network. An input node between the first and second pairs of transistors may be configured to receive an input current for the current mirror, and an output node at the first pair of transistors may be configured to sink an output current for the current mirror, proportional to the input current. This current mirror architecture offers a hybrid low-voltage/high-voltage solution, tolerates low input voltages, provides high output impedance, and offers low area and power consumption.

Abstract translation: 本公开的某些方面通常涉及低电压，精确的电流镜，其可用于集成电路（IC）中的远程电流的分布式感测。 一个示例电流镜通常包括第一对晶体管，与第一对晶体管共源共栅的第二对晶体管，耦合到第二对晶体管的开关网络和耦合到开关网络的第三对晶体管。 第一和第二对晶体管之间的输入节点可以被配置为接收电流镜的输入电流，并且第一对晶体管的输出节点可以被配置为吸收电流镜的输出电流，与 输入电流。 该电流镜架构提供混合低压/高压解决方案，可承受低输入电压，提供高输出阻抗，并提供低面积和功耗。

公开(公告)号：US20170085266A1

公开(公告)日：2017-03-23

申请号：US14862473

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Meysam ZARGHAM ,  Masoud ROHAM ,  Liang DAI

IPC: H03K19/0185

CPC classification number: H03K19/018528 ,  H03F1/0266 ,  H03F1/42 ,  H03F3/3028 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/18 ,  H03F2200/444 ,  H03K19/018521 ,  H03K19/018585

Abstract: Certain aspects of the present disclosure provide methods and apparatus (e.g., a level shifter) for buffering an oscillating signal generated by an oscillator. One example apparatus generally includes an amplifier having a first amplification stage configured to amplify the oscillating signal generated by the oscillator and a second amplification stage configured to amplify an inverse of the oscillating signal generated by the oscillator; and a sensing circuit configured to adjust an operational bandwidth of the amplifier based on a frequency of the oscillating signal.

公开(公告)号：US20240167889A1

公开(公告)日：2024-05-23

申请号：US17989614

申请日：2022-11-17

Applicant: QUALCOMM Incorporated

Inventor： Balasubramanian SIVAKUMAR ,  Liang DAI ,  Dinesh Jagannath ALLADI

IPC: G01K7/01

CPC classification number: G01K7/01

Abstract: A subthreshold-based MOSFET temperature sensor is provided for generating a subthreshold leakage current that is proportional to a difference between a gate-to-source voltage of a first transistor and a gate-to-source voltage of a second transistor. The subthreshold leakage current is mirrored to a detector for a temperature determination.

公开(公告)号：US20230253400A1

公开(公告)日：2023-08-10

申请号：US17650233

申请日：2022-02-07

Applicant: QUALCOMM Incorporated

Inventor： Bruce LEE ,  Chandra Satya Priyanka TIRUPATHI ,  Liang DAI ,  Dinesh Jagannath ALLADI

IPC: H01L27/07 ,  H01L27/08

CPC classification number: H01L27/0733 ,  H01L27/0805

Abstract: A device includes a first plurality of MEOL interconnects coupled to a second node that extends in a first direction. The first plurality of MEOL interconnects includes first and second subsets of MEOL second-terminal interconnects. The device includes a second plurality of MEOL interconnects coupled to a first node that extends in the first direction. The second plurality of MEOL interconnects includes first and second subsets of MEOL first-terminal interconnects. The first subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a first subset of interleaved MEOL interconnects. The second subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a second subset of interleaved MEOL interconnects. The device includes at least one of a first plurality of gate interconnects or a first plurality of OD regions extending in a second direction orthogonal to the first direction between the first and second subsets of interleaved MEOL interconnects.

公开(公告)号：US20150192943A1

公开(公告)日：2015-07-09

申请号：US14151701

申请日：2014-01-09

Applicant: QUALCOMM Incorporated

Inventor： Masoud ROHAM ,  Wei ZHENG ,  Liang DAI ,  Dinesh J. ALLADI ,  Yuhua GUO

IPC: G05F1/56

CPC classification number: G05F1/56 ,  G05F1/575

Abstract: Exemplary embodiments are related to voltage regulators. A device may include a first energy storage element coupled between a ground voltage and an output. The device may also include a second energy storage element coupled to the ground voltage and configured to selectively couple to the output. Further, the device may include a voltage regulator coupled between an input and the second energy storage element.

Abstract translation: 示例性实施例涉及电压调节器。 装置可以包括耦合在接地电压和输出之间的第一能量存储元件。 该装置还可以包括耦合到接地电压并被配置为选择性地耦合到输出的第二能量存储元件。 此外，该装置可以包括耦合在输入端和第二能量存储元件之间的电压调节器。

公开(公告)号：US20170093420A1

公开(公告)日：2017-03-30

申请号：US15014865

申请日：2016-02-03

Applicant: QUALCOMM Incorporated

Inventor： Omid RAJAEE ,  Liang DAI ,  Ganesh KIRAN

IPC: H03M1/38 ,  H03M1/10

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M1/1014 ,  H03M1/188

Abstract: Certain aspects of the present disclosure provide a segmented successive approximation register (SAR) analog-to-digital converter (ADC). One example ADC generally includes a plurality of SAR ADC circuits each associated with a different voltage range segment of a voltage range for the ADC. Each SAR ADC circuit is configured to receive an analog signal input to the ADC and to output a digital signal based on the analog signal, the digital signal being representative of a voltage level of the analog signal when the voltage level of the analog signal is within the segment associated with the SAR ADC circuit. In certain aspects, the SAR ADC may include logic configured to control a digital output of the ADC based on one or more of the digital signals representative of the voltage level of the analog signal output by one or more of the plurality of SAR ADC circuits.

公开(公告)号：US20150137201A1

公开(公告)日：2015-05-21

申请号：US14264620

申请日：2014-04-29

Applicant: QUALCOMM Incorporated

Inventor： Bruce Sokki LEE ,  Seyfollah Seyfollahi BAZARJANI ,  Liang DAI

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0733 ,  H01L28/60 ,  H01L28/86 ,  H01L28/92 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A methods for fabricating a capacitor structure includes fabricating polysilicon structures on a semiconductor substrate. The method further includes fabricating M1 to diffusion (MD) interconnects on the semiconductor substrate. The polysilicon structures are disposed in an interleaved arrangement with the MD interconnects. The method also includes selectively connecting the interleaved arrangement of the MD interconnects and/or the polysilicon structures as the capacitor structure.

Abstract translation: 制造电容器结构的方法包括在半导体衬底上制造多晶硅结构。 该方法还包括在半导体衬底上制造M1到扩散（MD）互连。 多晶硅结构以与MD互连的交错布置设置。 该方法还包括有选择地连接MD互连和/或多晶硅结构的交错布置作为电容器结构。