公开(公告)号：US09158720B2

公开(公告)日：2015-10-13

申请号：US13964089

申请日：2013-08-11

Applicant: Qualcomm Incorporated

Inventor： Martyn Ryan Shirlen ,  Victor Wong

IPC: G06F9/44 ,  G06F13/36 ,  G06F11/36 ,  G06F11/34

CPC classification number: G06F13/36 ,  G06F11/3466 ,  G06F11/364 ,  G06F11/3648 ,  G06F2201/835

Abstract: An integrated circuit includes a trace subsystem that provides timestamps for events occurring in a trace source that does not natively support time stamping trace data. A timestamp inserter is coupled to such a trace source. The timestamp inserter generates a modified trace data stream by arranging a reference or references with the trace information from the trace source on a trace bus. A trace destination receives the modified trace data stream including the reference(s). In some embodiments, a timestamp inserter receives a timestamp request and stores a reference in a buffer. Upon later receipt of trace information associated with the request, the timestamp inserter inserts the reference, a current reference and the received trace information into the trace data stream.

Abstract translation: 集成电路包括跟踪子系统，该跟踪子系统为不在本地支持时间戳跟踪数据的跟踪源中发生的事件提供时间戳。 时间戳插入器耦合到这样的跟踪源。 时间戳插入器通过在跟踪总线上布置来自跟踪源的跟踪信息的引用或引用来生成修改的跟踪数据流。 跟踪目的地接收包括参考的修改的跟踪数据流。 在一些实施例中，时间戳插入器接收时间戳请求并将参考存储在缓冲器中。 在稍后收到与请求相关联的跟踪信息之后，时间戳插入器将参考，当前参考和接收到的跟踪信息插入跟踪数据流。

公开(公告)号：US20150033082A1

公开(公告)日：2015-01-29

申请号：US13963292

申请日：2013-08-09

Applicant: QUALCOMM Incorporated

Inventor： Ryan Shirlen ,  Victor Wong

IPC: G06F11/07 ,  G06F13/40

CPC classification number: G06F11/0724 ,  G01R31/31705 ,  G06F11/2242 ,  G06F11/263 ,  G06F11/3656 ,  G06F13/4027 ,  G06F15/7807 ,  H04L5/22

Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.

Abstract translation: 实施例包括用于减少引脚交叉触发以增强调试体验的装置，系统和方法。 可以采用时分封装（TDP）技术来促进串联形成TDP通信环的集成电路（IC）之间的触发通信。 TDP通信环上的IC可以各自包括用于在触发信号和硬件核心指令之间解释的交叉触发互连结构。 TDP通信环路上的IC间的串行TDP通信允许以这样的方式连接IC，即每个IC上的每个交叉触发互连结构可以像在跨所有IC上的单个交叉触发互连结构的一部分一样起作用 TDP通信环。 单个IC可以异步操作，并且触发时钟可以与其他触发数据一起传递，以在每个IC上均匀地实现调试技术。

公开(公告)号：US20140245076A1

公开(公告)日：2014-08-28

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/30

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。

公开(公告)号：US09304844B2

公开(公告)日：2016-04-05

申请号：US13779627

申请日：2013-02-27

Applicant: QUALCOMM Incorporated

Inventor： Kapil Bansal ,  Girish Bhat ,  Subodh Singh ,  Victor Wong ,  Pradeep Atur

IPC: G06F11/36 ,  G06F11/07

CPC classification number: G06F11/0742 ,  G06F11/0757 ,  G06F11/3648 ,  G06F11/3656 ,  G06F11/366

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract translation: 一个或多个触发器可以耦合到便携式计算设备的芯片上的系统上的源。 来源监视系统的状态条件。 一个或多个触发器耦合到触发总线。 定序器引擎耦合到触发总线和通信总线。 定序器引擎从通信总线接收一个或多个指令，用于确定定序器引擎如何经由触发总线监视一个或多个触发，并在系统复位之前保留从一个或多个触发器接收到的数据。 然后，定序器引擎从一个或多个触发器接收数据，并将数据存储在本地存储器中。 响应于从一个或多个触发器接收数据，定序器引擎（如果编程的话）可以产生跟踪数据包，中断信号和通用输入/输出信号中的至少一个。

公开(公告)号：US09208008B2

公开(公告)日：2015-12-08

申请号：US13963292

申请日：2013-08-09

Applicant: QUALCOMM Incorporated

Inventor： Ryan Shirlen ,  Victor Wong

IPC: G06F11/22 ,  G06F11/07 ,  G06F13/40 ,  G01R31/317 ,  G06F11/36 ,  G06F11/263 ,  H04L5/22 ,  G06F15/78

CPC classification number: G06F11/0724 ,  G01R31/31705 ,  G06F11/2242 ,  G06F11/263 ,  G06F11/3656 ,  G06F13/4027 ,  G06F15/7807 ,  H04L5/22

Abstract: Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.

Abstract translation: 实施例包括用于减少引脚交叉触发以增强调试体验的装置，系统和方法。 可以采用时分封装（TDP）技术来促进串联形成TDP通信环的集成电路（IC）之间的触发通信。 TDP通信环上的IC可以各自包括用于在触发信号和硬件核心指令之间解释的交叉触发互连结构。 TDP通信环路上的IC间的串行TDP通信允许以这样的方式连接IC，即每个IC上的每个交叉触发互连结构可以像在跨所有IC上的单个交叉触发互连结构的一部分一样起作用 TDP通信环。 单个IC可以异步操作，并且触发时钟可以与其他触发数据一起传递，以在每个IC上均匀地实现调试技术。