公开(公告)号：US20170223646A1

公开(公告)日：2017-08-03

申请号：US15251581

申请日：2016-08-30

Applicant: QUALCOMM Incorporated

Inventor： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

IPC: H04W56/00 ,  H04W52/02 ,  H04L7/02

CPC classification number: H04W56/001 ,  G06F13/4273 ,  H04L7/02 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/164 ,  Y02D70/26

Abstract: Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

公开(公告)号：US10159053B2

公开(公告)日：2018-12-18

申请号：US15251581

申请日：2016-08-30

Applicant: QUALCOMM Incorporated

Inventor： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

IPC: H04W56/00 ,  H04L7/02 ,  H04W52/02 ,  G06F13/42

Abstract: Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

公开(公告)号：US09979432B2

公开(公告)日：2018-05-22

申请号：US15420520

申请日：2017-01-31

Applicant: QUALCOMM Incorporated

Inventor： Raheel Khan ,  Scott Cheng ,  Pascal Philippe ,  Graig Zethner ,  Vaidyanathan Seetharaman ,  Kanwal Preet S. Banga ,  Srinivas Badam

IPC: H04B1/38 ,  H04B1/40 ,  H04L29/08

CPC classification number: H04B1/40 ,  H04B17/318 ,  H04L69/323 ,  H04L69/324

Abstract: A serial transceiver that includes programmable distributed data processing is provided. The serial transceiver can include an ingress channel that receives serial ingress data and an egress channel that transmits serial egress data. The serial transceiver can also include first and second layers that are one and another of a transport layer, a link layer, or a physical layer (PHY). The first and second layers can include elements that process the ingress data and the egress data. The serial transceiver can also include a programmable controller, a first interconnect that connects the programmable controller to the first layer, and a second interconnect that connects the programmable controller to the second layer. The programmable controller can send first data via the first interconnect to the first layer, and the first data can be processed by one of the first layer elements.