公开(公告)号：US10159053B2

公开(公告)日：2018-12-18

申请号：US15251581

申请日：2016-08-30

申请人： QUALCOMM Incorporated

发明人： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

IPC分类号： H04W56/00 ,  H04L7/02 ,  H04W52/02 ,  G06F13/42

摘要： Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.

公开(公告)号：US10423567B2

公开(公告)日：2019-09-24

申请号：US15422263

申请日：2017-02-01

申请人： QUALCOMM Incorporated

发明人： Raheel Khan ,  Scott Cheng ,  Pascal Philippe ,  Joaquin Romera

IPC分类号： H04L12/931 ,  G06F13/42 ,  G06F13/364 ,  G06F9/00 ,  H04B1/40 ,  H04L7/00 ,  H04L29/06 ,  H04L29/08 ,  H04L7/04

摘要： Transmission of data over a serial link based on a unidirectional clock signal is provided. A unidirectional clock signal is generated based on a first clock of a master device. The unidirectional clock signal is sent to a slave device that is connected to the serial link. The master device transmits data to the slave device over the serial link based on the first clock. The slave device receives the unidirectional clock signal from a master device. The slave device transmits data over the serial link to the master device based on the unidirectional clock signal.

公开(公告)号：US20170223646A1

公开(公告)日：2017-08-03

申请号：US15251581

申请日：2016-08-30

申请人： QUALCOMM Incorporated

发明人： Joaquin Romera ,  Graig Zethner ,  Raheel Khan

IPC分类号： H04W56/00 ,  H04W52/02 ,  H04L7/02

CPC分类号： H04W56/001 ,  G06F13/4273 ,  H04L7/02 ,  H04W52/0235 ,  Y02D70/122 ,  Y02D70/164 ,  Y02D70/26

摘要： Systems, methods, and apparatus for synchronizing timing in devices coupled to a data communication link are disclosed. In one example, a first device programs a future system time value in a second device. The first device launches a low-latency trigger signal that causes the future system time value to be loaded into a timer of the second device when a timer of the first device matches the future system time value. The second device measures phase difference between the trigger signal and edges of a clock signal used for timing in the second device. The phase difference is measured using an oversampling clock that provides a desired measurement reliability. The measured phase difference permits the first device to accurately determine system time as applied to the second device. The trigger signal can be provided on existing pins used by first and second devices in accordance with communication protocols and specifications.