公开(公告)号：US11935606B2

公开(公告)日：2024-03-19

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Sahu ,  Sharad Kumar Gupta ,  Jung Pill Kim ,  Chulmin Jung ,  Jais Abraham

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US10656203B1

公开(公告)日：2020-05-19

申请号：US16278420

申请日：2019-02-18

Applicant: QUALCOMM Incorporated

Inventor： Punit Kishore ,  Jais Abraham ,  Pawan Chhabra

IPC: G01R31/317 ,  G06F13/42 ,  G01R31/3177 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.

公开(公告)号：US10996267B2

公开(公告)日：2021-05-04

申请号：US16255214

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jais Abraham ,  Punit Kishore

IPC: G01R31/317 ,  G01R31/3185

Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.