公开(公告)号：US11237587B1

公开(公告)日：2022-02-01

申请号：US17121580

申请日：2020-12-14

Applicant: QUALCOMM Incorporated

Inventor： Punit Kishore ,  Ankit Goyal ,  Srinivas Patil

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/14

Abstract: Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.

公开(公告)号：US10656203B1

公开(公告)日：2020-05-19

申请号：US16278420

申请日：2019-02-18

Applicant: QUALCOMM Incorporated

Inventor： Punit Kishore ,  Jais Abraham ,  Pawan Chhabra

IPC: G01R31/317 ,  G06F13/42 ,  G01R31/3177 ,  H03K19/20

Abstract: Certain aspects of the present disclosure provide an apparatus for processor core testing. The apparatus generally includes a high-speed input-output (HSIO) interface, a general purpose input-output (GPIO) interface, a multiplexer having a first input coupled to the GPIO interface, a test controller coupled between the HSIO interface and a second input of the multiplexer, and one or more processor cores coupled to the output of the multiplexer.

公开(公告)号：US10996267B2

公开(公告)日：2021-05-04

申请号：US16255214

申请日：2019-01-23

Applicant: QUALCOMM Incorporated

Inventor： Jais Abraham ,  Punit Kishore

IPC: G01R31/317 ,  G01R31/3185

Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.