公开(公告)号：US20170149555A1

公开(公告)日：2017-05-25

申请号：US14947278

申请日：2015-11-20

Applicant: QUALCOMM Incorporated

Inventor： Hanan Cohen ,  Jason Thurston

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0332 ,  H04L1/205 ,  H04L1/243 ,  H04L7/0008 ,  H04L7/0012 ,  H04L7/0025 ,  H04L7/0334 ,  H04L7/0337

Abstract: A source-synchronous system is provided in which a master device is configured to vary the phase between a transmitted data signal and a corresponding source-synchronous clock to measure the margins of a data eye at a slave device.

公开(公告)号：US09633698B2

公开(公告)日：2017-04-25

申请号：US14280313

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Vaishnav Srinivas ,  David Ian West ,  Deepti Vijayalakshmi Sriramagiri ,  Jungwon Suh ,  Jason Thurston

IPC: G06F11/00 ,  G11C5/14 ,  G06F11/07 ,  G06F11/10 ,  G01R31/317

CPC classification number: G11C5/147 ,  G01R31/31709 ,  G01R31/3171 ,  G06F11/076 ,  G06F11/1004

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

公开(公告)号：US09236884B2

公开(公告)日：2016-01-12

申请号：US13929728

申请日：2013-06-27

Applicant: QUALCOMM Incorporated

Inventor： Hans Georg Gruber ,  Subra Dravida ,  Parvathanathan Subrahmanya ,  Vidyut Mukund Naware ,  Helena Deirdre O'Shea ,  Garret Webster Shih ,  Jason Thurston

IPC: H03M13/09 ,  H03M13/00 ,  H04L1/00

CPC classification number: H03M13/09 ,  H04L1/004 ,  H04L1/0061 ,  H04L1/0072

Abstract: A method, an apparatus, and a computer program product for communication within a wireless terminal. The method can be implemented using dedicated logic and managed and controlled by state machines and/or sequencers. Data received or provided in a memory of a first integrated circuit of a terminal is encoded and transmitted in a data packet to a second integrated circuit. A header identifying the data type and providing a destination is included in the data packet. The destination may be identified as a memory address memory of the second integrated circuit that is mapped to a corresponding memory address of the first integrated circuit at which the data is received. In an aspect, the apparatus receives a header, detects an error in the received header, determines a failure to identify a packet boundary when the error is detected, and performs a search operation to identify the packet boundary.

Abstract translation: 一种用于在无线终端内进行通信的方法，装置和计算机程序产品。 该方法可以使用专用逻辑来实现，并由状态机和/或定序器进行管理和控制。 接收或提供在终端的第一集成电路的存储器中的数据被编码并在数据分组中发送到第二集成电路。 识别数据类型并提供目的地的报头被包括在数据分组中。 目的地可以被识别为第二集成电路的存储器地址存储器，其被映射到接收数据的第一集成电路的相应存储器地址。 一方面，该装置接收报头，检测出接收到的报头中的错误，确定检测到错误时识别分组边界的故障，并执行识别分组边界的搜索操作。