公开(公告)号：US20160246721A1

公开(公告)日：2016-08-25

申请号：US14626913

申请日：2015-02-19

Applicant: QUALCOMM Incorporated

Inventor： Phil Joseph BOSTLEY, III ,  Jaya Prakash Subramaniam GANASAN

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/455

CPC classification number: G06F12/0828 ,  G06F9/45558 ,  G06F9/466 ,  G06F12/0811 ,  G06F12/0833 ,  G06F2009/45587 ,  G06F2212/1028 ,  G06F2212/152 ,  G06F2212/283 ,  G06F2212/622 ,  Y02D10/13

Abstract: A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.

Abstract translation: 描述了一种基于事务属性来控制缓存窥探和/或使特定高速缓存的相干流量无效的方法。 存储器管理单元（MMU）从请求处理器确定用于高速缓存一致性事务的一个或多个事务属性。 路由模块基于事务属性识别可访问域和/或可共享域，并将高速缓存一致性事务路由到可缓存域和/或可共享域中的一个或多个高速缓存。 代替一致性流量被路由到相干总线上的所有高速缓存，相干流量基于诸如地址空间标识符（ASID），虚拟机器标识符（VMID），安全位（NS），管理程序 标识符（HYP）等

公开(公告)号：US20150074357A1

公开(公告)日：2015-03-12

申请号：US14195792

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Joseph G. MCDONALD ,  Jaya Prakash Subramaniam GANASAN ,  Thomas Philip SPEIER ,  Eric F. ROBINSON ,  Jason Lawrence PANAVICH ,  Thuong Q. TRUONG

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0824 ,  G06F12/0833 ,  G06F2212/1024 ,  G06F2212/1041

Abstract: A low latency cache intervention mechanism implements a snoop filter to dynamically select an intervener cache for a cache “hit” in a multiprocessor architecture of a computer system. The selection of the intervener is based on variables such as latency, topology, frequency, utilization, load, wear balance, and/or power state of the computer system.

Abstract translation: 低延迟高速缓存干预机制实现了窥探过滤器来动态地选择用于计算机系统的多处理器架构中的高速缓存“命中”的intervener缓存。 干扰器的选择基于诸如延迟，拓扑，频率，利用率，负载，磨损平衡和/或计算机系统的功率状态等变量。

公开(公告)号：US20170075838A1

公开(公告)日：2017-03-16

申请号：US14853066

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Prudhvi Nadh NOONEY ,  Jaya Prakash Subramaniam GANASAN

IPC: G06F13/37 ,  G06F13/40 ,  G06F13/362

CPC classification number: G06F13/37 ,  G06F13/362 ,  G06F13/4004 ,  H04L45/302 ,  H04L49/1515 ,  H04L49/205

Abstract: Techniques are disclosed to provide quality of service in bus interconnects with multi-stage arbitration. Source computing elements tag packets with a priority class and/or a number of credits that are based on a distance to a destination computing element of the packets. Arbiters controlling access to the bus interconnect perform arbitration operations to serve packets having higher relative priority based on the priority levels and/or numbers of credits of each packet.

Abstract translation: 公开了提供具有多级仲裁的总线互连中的服务质量的技术。 源计算元件标记具有基于距分组的目的地计算元素的距离的优先级等级和/或信用数量的分组。 控制对总线互连的访问的仲裁器执行仲裁操作，以基于每个分组的优先级和/或信用数来提供具有较高相对优先级的分组。