公开(公告)号：US09722335B2

公开(公告)日：2017-08-01

申请号：US14270156

申请日：2014-05-05

申请人： QUALCOMM Incorporated

发明人： Robert Walter Berry, Jr. ,  Ryan Joseph Pennington ,  Joab Daniel Henderson ,  Divya Kumar

IPC分类号： G06F11/07 ,  H01R12/70 ,  G06F11/20 ,  G06F13/16 ,  G06F13/40

CPC分类号： H01R12/7076 ,  G06F11/008 ,  G06F11/07 ,  G06F11/2094 ,  G06F13/1668 ,  G06F13/409 ,  G11C5/04 ,  G11C29/781 ,  G11C29/832

摘要： An enhanced dual in line memory module (DIMM) connector includes internal conductive paths that provide access to signaling on standard conductive paths to an industry standard DIMM. The internal conductive paths are coupled in series or in parallel with the standard conductive paths through the connector. Interposer circuitry, such as control circuitry and or supplemental memory circuitry, may be incorporated on or within the connector. The interposer circuitry may include field effect transistor (FET) switching circuitry configured to selectively decouple a defective dynamic random memory (DRAM) on a DIMM from a conductive path to a memory controller and couple a substitute DRAM to the conductive paths in its place.

公开(公告)号：US20170046212A1

公开(公告)日：2017-02-16

申请号：US14825495

申请日：2015-08-13

申请人： QUALCOMM Incorporated

发明人： Carlos Alberto Fernandez ,  Joab Daniel Henderson ,  Michael Louis Hobbs

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/079 ,  G06F3/0617 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1666 ,  G06F13/00 ,  G11C29/00 ,  G11C29/76

摘要： Reducing system downtime during memory subsystem maintenance in a computer processing system is disclosed. In some aspects, a computer processing system comprises a computer processor communicatively coupled to a plurality of memory sockets, each of which interfaces with a memory module and includes a gate control. The computer processor is further communicatively coupled to a dedicated non-volatile storage device. Upon detection of a memory health condition requiring replacement of a memory module, access to the memory module is blocked, and data is transferred from the memory module to the dedicated non-volatile storage device. A memory address range of the memory module is then remapped to the dedicated non-volatile storage device, such that subsequent memory access requests to the memory module are rerouted to the dedicated non-volatile storage device. The memory socket of the memory module is then gated, allowing maintenance to be performed while maintaining system availability.

摘要翻译： 公开了在计算机处理系统中的存储器子系统维护期间减少系统停机时间。 在一些方面，计算机处理系统包括通信地耦合到多个存储器插槽的计算机处理器，每个存储器插槽与存储器模块接口并且包括门控制。 计算机处理器进一步通信地耦合到专用非易失性存储设备。 在检测到需要更换存储器模块的存储器健康状况时，对存储器模块的访问被阻止，并且数据从存储器模块传送到专用非易失性存储设备。 然后将存储器模块的存储器地址范围重新映射到专用非易失性存储设备，使得对存储器模块的后续存储器访问请求被重新路由到专用非易失性存储设备。 然后将存储器模块的存储器插槽选通，允许在保持系统可用性的同时执行维护。