公开(公告)号：US20240297654A1

公开(公告)日：2024-09-05

申请号：US18177445

申请日：2023-03-02

Applicant: QUALCOMM Incorporated

Inventor： John ABCARIUS ,  Debesh BHATTA ,  Andrew WEIL ,  Robert Martin ONDRIS ,  Wenjing YIN

IPC: H03L7/099

CPC classification number: H03L7/0992

Abstract: Certain aspects of the present disclosure provide a relatively compact frequency-locked loop (FLL) using a discrete-time integrator. For certain aspects, the FLL also includes a supplemental oscillator and other circuitry that allows for saving the FLL frequency when a reference clock will be disconnected, maintaining a similar frequency during disconnection, and restoring the FLL frequency when the reference clock is reconnected. One example FLL circuit generally includes: an encoder; a combiner comprising a first input coupled to an output of the encoder; a digital-to-analog converter (DAC) comprising an input coupled to an output of the combiner; a discrete-time integrator comprising an input coupled to an output of the DAC; a voltage-controlled oscillator (VCO) comprising a control input coupled to an output of the discrete-time integrator; and a counter comprising an input coupled to an output of the VCO and comprising an output coupled to a second input of the combiner.

公开(公告)号：US20210075434A1

公开(公告)日：2021-03-11

申请号：US16563083

申请日：2019-09-06

Applicant: QUALCOMM Incorporated

Inventor： Debesh BHATTA ,  Kevin Jia-Nong WANG ,  Karthik NAGARAJAN ,  John ABCARIUS ,  Andrew WEIL ,  Christian VENERUS ,  Jeffrey Mark HINRICHS

IPC: H03M1/06 ,  H03M1/70 ,  H03C3/09

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for digital-to-analog conversion. One example apparatus generally includes a first digital-to-analog converter (DAC) having an input coupled to a digital input node of the apparatus, a second DAC, a digital processor coupled between the digital input node and an input of the second DAC, and a combiner coupled to the first DAC and the second DAC.

公开(公告)号：US20190028109A1

公开(公告)日：2019-01-24

申请号：US15863672

申请日：2018-01-05

Applicant: QUALCOMM Incorporated

Inventor： John ABCARIUS

IPC: H03L7/089 ,  H03L7/093 ,  H04L27/148 ,  H04L27/152

CPC classification number: H03L7/0891 ,  H03L7/0893 ,  H03L7/093 ,  H04L27/148 ,  H04L27/152

Abstract: A phase locked loop (PLL) includes a first charge pump coupled to a filter. The first charge pump may feed the filter a first current. A second charge pump is coupled to the filter. The second charge pump may feed the filter a second current. A first gate is coupled to an input of the second charge pump. The first gate selectively gates the second current.